EasyManuals Logo

Broadcom NetXtreme/NetLink BCM5718 Series User Manual

Broadcom NetXtreme/NetLink BCM5718 Series
593 pages
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Page #434 background imageLoading...
Page #434 background image
RDMA RegistersBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 5718-PG108-R Page 434
PCI Request Burst Length for
LSO engine
17:16 RW 0 The two bits define the burst length that the
RDMA read engine would request to the PCI
block.
00 = 128B
01 = 256B
10 = 512B
•11 = 4KB
Note: The actual size of the resulting PCIe
memory read transaction may be further limited
by the PCIe Maximum Read Request Size
(MRRS) field of the PCIe Device Status Control
Register (0xB4).
Reserved 15:11 RO 0
Read DMA PCI-X Split
Transaction Timeout Expired
Attention Enable
10 RW 0 Enable read DMA PCI-X split transaction timeout
expired attention.
Read DMA Local Memory
Write Longer Than DMA
Length Attention Enable
9 RW 0 Enable Read DMA Local Memory Write Longer
Than DMA Length Attention.
Read DMA PCI FIFO Overread
Attention Enable
8 RW 0 Enable Read DMA PCI FIFO Overread Attention
(PCI read longer than DMA length.)
Read DMA PCI FIFO Underrun
Attention Enable
7 RW 0 Enable Read DMA PCI FIFO Underrun Attention.
Read DMA PCI FIFO Overrun
Attention Enable
6 RW 0 Enable Read DMA PCI FIFO Overrun Attention.
Read DMA PCI Host Address
Overflow Error Attention
Enable
5 RW 0 Enable Read DMA PCI Host Address Overflow
Error Attention. A host address overflow occurs
when a single DMA read begins at an address
below 4 GB and ends on an address above 4 GB.
This is a fatal error.
Read DMA PCI Parity Error
Attention Enable
4 RW 0 Enable Read DMA PCI Parity Error Attention.
Read DMA PCI Master Abort
Attention Enable
3 RW 0 Enable Read DMA PCI Master Abort Attention.
Read DMA PCI Target Abort
Attention Enable
2 RW 0 Enable Read DMA PCI Target Abort Attention.
Enable 1 RW 1 This bit controls whether the Read DMA state
machine is active or not. When set to 0, it
completes the current operation and cleanly
halts. Until it is completely halted, it remains one
when read.
Reset 0 RW 0 When this bit is set to 1, the Read DMA state
machine is reset. This is a self-clearing bit.
Name Bits Access
Default
Value
Description

Table of Contents

Questions and Answers:

Question and Answer IconNeed help?

Do you have a question about the Broadcom NetXtreme/NetLink BCM5718 Series and is the answer not in the manual?

Broadcom NetXtreme/NetLink BCM5718 Series Specifications

General IconGeneral
BrandBroadcom
ModelNetXtreme/NetLink BCM5718 Series
CategoryController
LanguageEnglish

Related product manuals