10h–1Fh Register Map Detailed DescriptionBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 531
7:6 SERDES SPEED RO 10 = SerDes speed 1000 (SGMII 1000 or
1000X)
01 = SerDes speed 100 (SGMII 100 or 100fx)
00 = SerDes speed 10 (SGMII 10)
10
5 SERDES LINK STATUS
CHANGE
RO
LH
1 = link status change detected since last read
0 = link status change not detected since last
read
0
4:3 MODE SELECT RO 00 = copper
01 = fiber
10 = SGMII
11 = GBIC
00000
2 RGMII/MII ->
SGMII SLAVE 10/100
TX FIFO
FREQUENCY LOCK
MODE
(forced high internally
when =>
sgmii_slave_mode and not
rgmii_mode and not
remote_lpbk)
RW 1 = SGMII transmit FIFO will assume that the
SerDes
pll clock and the MAC transmit clock are
frequency locked. This will essentially bypass
the FIFO with the lowest possible latency in 10/
100 speeds.
(useful for applications where the MAC is in
RGMII mode and the PHY is in RGMII-> SGMII
slave mode, and both the MAC and PHY are
using the same crystal. When the MAC is in MII
mode and the PHY is in MII->SGMII slave
mode, then this bit should always be set.)
0 = normal operation
00000
1 SGMII SLAVE MODE
(register 1c shadow 1fh
bit [2:1] must be “01”)
RW 1 = enable MII/GMII/RGMII -> SGMII mode
(only slave mode supported; useful for MAC
RGMII to SGMII conversions, which are
attached to an external phy.)
0 = disable SGMII slave mode
00000
0 SGMII SLAVE AUTO-
DETECTION
(register 1c shadow 1fh
bit [2] must be 0)
RW 1 = enable SGMII slave auto-detection.
Switch between 1000-X and SGMII slave
modes based on SerDes received auto-
negotiation code word.
0 = normal operation
00000
Bit Name RW Description Default
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