Revision HistoryBCM5718 Programmer’s Guide
Broadcom®
January 29, 2016 • 5718-PG108-R Page 7
• “Receive Max Coalesced BD Count During Interrupt Register (offset:
0x3C18)” on page 424
• “Send Max Coalesced BD Count During Interrupt Register (offset:
0x3C1C)” on page 425
• “NIC Mini Receive BD Consumer Index (offset: 0x3c58)” on page 428
• “Send BD Ring Producer Index Register (offset: 0x5980)” on page 471
• “DMA Completion Mode Register (Offset: 0x6400)” on page 477
• Figure 58: “Copper PHY Register Mapping Table,” on page 511
• Figure 59: “SerDes PHY Register Map,” on page 512
• “Clause 45 Registers” on page 601
• “SerDes PHY Register Definitions” on page 578
• “PHY 0x18 Shadow 0x1 register read Procedure” on page 527
• Added PHY 0x1C Shadow 0x1 register read Procedure information to
“1Ch: Cabletron LED Register (Shadow Register Selector = “00h”)” on
page 538
• Added Clause 45 register Dev3 Reg803Eh read Procedure to “Clause 45
Register Dev 3 Reg14h (20d): EEE Capability Register” on page 601
• NIC Ring Addresses information to Memory map tables in
Appendix C: “Device Register and Memory Map,” on page 611
Deleted
• Section 11: Host to/from BMC Pass Through
• Appendix D: Appendix
• Top Level MII Registers
5718-PG104-R 06/29/11 Updated:
• Table 27: “Flag Field Description,” on page 113
• Table 31: “Send Buffer Descriptor Flags,” on page 123
• “Clock Control” on page 191
• Table 47: “Ethernet Controller Power Pins,” on page 191
• “Internal Memory” on page 214
• “ISR Flow” on page 230
• Table 82: “Interrupt-Related Registers,” on page 235
• “Status Register (offset: 0x362C)” on page 391
• “Clock Status Register (offset: 0x3630)” on page 393
• “LSO Read DMA Mode Register (offset: 0x4800)” on page 438
• “NVM Write Register (offset: 0x7008)” on page 497
Added:
• “Device Closing Procedure” on page 147
• “TX TIME STAMP LSB REG (offset: 0x5C0)” on page 327
• “TX TIME STAMP MSB REG (offset: 0x5C4)” on page 327
Revision Date Change Description
To Next Page
Loading...
Need help?
General
