Freescale Semiconductor PowerPC e500 Core - Page 23

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xxiii
Figures
Figure
Number Title
Page
Number
7-2 Local Control A Registers (PMLCa0–PMLCa3)/
User Local Control A Registers (UPMLCa0–UPMLCa3) ................................................ 7-5
7-3 Local Control B Registers (PMLCb0–PMLCb3)/
User Local Control B Registers (UPMLCb0–UPMLCb3) ................................................ 7-7
7-4 Performance Monitor Counter Registers (PMC0–PMC3)/
User Performance Monitor Counter Registers (UPMC0–UPMC3)...................................7-8
8-1 TAP Controller with Supported Registers............................................................................... 8-4
9-1 Relationship of Timer Facilities to Time Base........................................................................ 9-2
10-1 Vector and Floating-Point APUs........................................................................................... 10-2
10-2 Floating-Point Data Format .................................................................................................. 10-5
11-1 Cache/Core Interface Unit Integration.................................................................................. 11-3
11-2 L1 Data Cache Organization................................................................................................. 11-6
11-3 L1 Instruction Cache Organization ....................................................................................... 11-7
11-4 PLRU Replacement Algorithm........................................................................................... 11-26
12-1 Effective-to-Real Address Translation Flow (e500v1)......................................................... 12-4
12-2 Effective-to-Real Address Translation Flow (e500v2)......................................................... 12-5
12-3 Virtual Address and TLB-Entry Compare Process............................................................... 12-7
12-4 Two-Level MMU Structure................................................................................................... 12-8
12-5 L1 MMU TLB Organization............................................................................................... 12-10
12-6 L2 MMU TLB Organization—e500v1............................................................................... 12-11
12-7 L2 MMU TLB Organization—e500v2............................................................................... 12-12
12-8 Round Robin Replacement for TLB0—e500v1 ................................................................. 12-14
12-9 Round Robin Replacement for TLB0—e500v2 ................................................................. 12-14
12-10 L1 MMU TLB Relationships with L2 TLBs ...................................................................... 12-15
12-11 MAS Register 0 (MAS0) .................................................................................................... 12-26
12-12 MAS Register 1 (MAS1) .................................................................................................... 12-27
12-13 MAS Register 2 (MAS2) .................................................................................................... 12-28
12-14 MAS Register 3 (MAS3) .................................................................................................... 12-29
12-15 MAS Register 4 (MAS4) .................................................................................................... 12-30
12-16 MAS Register 6 (MAS6) .................................................................................................... 12-31
12-17 MAS Register 7 (MAS7) .................................................................................................... 12-31
13-1 CCB Interface Signals........................................................................................................... 13-2
C-1 Branch Conditional (bc) Instruction Format...........................................................................C-4
C-2 BO Field (Bits 6–10 of the Instruction Encoding)..................................................................C-6
C-3 BI Field (Bits 11–14 of the Instruction Encoding)..................................................................C-9