Freescale Semiconductor PowerPC e500 Core - Page 22

PowerPC e500 Core Family Reference Manual, Rev. 1
xxii Freescale Semiconductor
Figures
Figure
Number Title
Page
Number
2-29 MAS Register 0 (MAS0) ...................................................................................................... 2-40
2-30 MAS Register 1 (MAS1) ...................................................................................................... 2-41
2-31 MAS Register 2 (MAS2) ...................................................................................................... 2-42
2-32 MAS Register 3 (MAS3) ...................................................................................................... 2-43
2-33 MAS Register 4 (MAS4) ...................................................................................................... 2-43
2-34 MAS Register 6 (MAS6) ...................................................................................................... 2-44
2-35 MAS Register 7 (MAS7) ...................................................................................................... 2-45
2-36 Debug Control Register 2 (DBCR2)..................................................................................... 2-47
2-37 Debug Status Register (DBSR)............................................................................................. 2-48
2-38 Signal Processing and Embedded Floating-Point Status and Control
Register (SPEFSCR) ........................................................................................................ 2-50
2-39 Performance Monitor Global Control Register 0 (PMGC0)/
User Performance Monitor Global Control Register 0 (UPMGC0) ................................ 2-53
2-40 Local Control A Registers (PMLCa0–PMLCa3)/
User Local Control A Registers (UPMLCa0–UPMLCa3) .............................................. 2-55
2-41 Local Control B Registers (PMLCb0–PMLCb3)/
User Local Control B Registers (UPMLCb0–UPMLCb3) .............................................. 2-56
2-42 Performance Monitor Counter Registers (PMC0–PMC3)/
User Performance Monitor Counter Registers (UPMC0–UPMC3).................................2-57
3-1 Register Indirect with Immediate Index Addressing for Integer Loads/Stores..................... 3-18
3-2 Register Indirect with Index Addressing for Integer Loads/Stores....................................... 3-19
3-3 Register Indirect Addressing for Integer Loads/Stores.........................................................3-20
3-4 SPE and Floating-Point APU GPR Usage ............................................................................ 3-50
3-5 Integer and Fractional Operations......................................................................................... 3-52
4-1 Instruction Flow Pipeline Diagram Showing Pipeline Stages ................................................ 4-4
4-2 e500 Instruction Flow Diagram—Details............................................................................... 4-5
4-3 GPR Issue Queue (GIQ) ......................................................................................................... 4-7
4-4 Execution Pipeline Stages and Events .................................................................................... 4-9
4-5 Execution Stages................................................................................................................... 4-10
4-6 Branch Completion (LR/CTR Write-Back) .......................................................................... 4-19
4-7 Updating Branch History ......................................................................................................4-20
4-8 Fetch Groups and Cache Line Alignment............................................................................. 4-21
4-9 Fetch Group Addresses ......................................................................................................... 4-22
4-10 Cache/Core Interface Unit Integration.................................................................................. 4-26
4-11 MU Divide Bypass Path (Showing an 11-Cycle Divide)...................................................... 4-28
6-1 Core Power Management State Diagram................................................................................ 6-2
6-2 Example Core Power Management Handshaking .................................................................. 6-5
7-1 Performance Monitor Global Control Register 0 (PMGC0)/
User Performance Monitor Global Control Register 0 (UPMGC0) .................................. 7-4