Freescale Semiconductor PowerPC e500 Core - Page 21

PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor xxi
Figures
Figure
Number Title
Page
Number
Figures
1-1 e500 Core Complex Block Diagram....................................................................................... 1-2
1-2 Vector and Floating-Point APUs............................................................................................. 1-6
1-3 Four-Stage MU Pipeline, Showing Divide Bypass................................................................. 1-8
1-4 Three-Stage Load/Store Unit ..................................................................................................1-9
1-5 Instruction Pipeline Flow......................................................................................................1-16
1-6 GPR Issue Queue (GIQ) ....................................................................................................... 1-17
1-7 e500 Core Programming Model............................................................................................ 1-19
1-8 MMU Structure ..................................................................................................................... 1-25
1-9 Effective-to-Real Address Translation Flow......................................................................... 1-26
1-10 Effective-to-Real Address Translation Flow (e500v2)......................................................... 1-27
2-1 e500 Register Model............................................................................................................... 2-3
2-2 Machine State Register (MSR) ............................................................................................. 2-10
2-3 Processor Version Register (PVR) ........................................................................................ 2-13
2-4 System Version Register (SVR)............................................................................................ 2-13
2-5 Relationship of Timer Facilities to the Time Base................................................................ 2-14
2-6 Timer Control Register (TCR).............................................................................................. 2-15
2-7 Alternate Time Base Register Lower (ATBL) ...................................................................... 2-17
2-8 Alternate Time Base Register Upper (ATBU) ...................................................................... 2-17
2-9 Interrupt Vector Offset Registers (IVORs) ........................................................................... 2-19
2-10 Exception Syndrome Register (ESR).................................................................................... 2-20
2-11 Machine Check Save/Restore Register 0 (MCSRR0)...........................................................2-22
2-12 Machine Check Save/Restore Register 1 (MCSRR1)...........................................................2-22
2-13 Machine Check Address Register (MCAR).......................................................................... 2-22
2-14 Machine Check Syndrome Register (MCSR)....................................................................... 2-23
2-15 Branch Buffer Entry Address Register (BBEAR) ................................................................ 2-25
2-16 Branch Buffer Target Address Register (BBTAR)................................................................ 2-25
2-17 Branch Unit Control and Status Register (BUCSR) ............................................................. 2-26
2-18 Hardware Implementation-Dependent Register 0 (HID0).................................................... 2-27
2-19 Hardware Implementation-Dependent Register 1 (HID1).................................................... 2-29
2-20 L1 Cache Control and Status Register 0 (L1CSR0).............................................................. 2-31
2-21 L1 Cache Control and Status Register 1 (L1CSR1).............................................................. 2-33
2-22 L1 Cache Configuration Register 0 (L1CFG0)..................................................................... 2-34
2-23 L1 Cache Configuration Register 1 (L1CFG1)..................................................................... 2-35
2-24 Process ID Registers (PID0–PID2)....................................................................................... 2-36
2-25 MMU Control and Status Register 0 (MMUCSR0) ............................................................. 2-36
2-26 MMU Configuration Register (MMUCFG) ......................................................................... 2-37
2-27 TLB Configuration Register 0 (TLB0CFG) ......................................................................... 2-38
2-28 TLB Configuration Register 1 (TLB1CFG) ......................................................................... 2-39