Freescale Semiconductor PowerPC e500 Core

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PowerPC e500 Core Family Reference Manual, Rev. 1

xx Freescale Semiconductor

Contents

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Number Title

Page

Number

C.4.3 Incorporating the BO Branch Prediction .....................................................................C-7

C.4.4 The BI Operand—CR Bit and Field Representations..................................................C-8

C.4.4.1 BI Operand Instruction Encoding............................................................................C-8

C.4.4.1.1 Specifying a CR Bit.............................................................................................C-9

C.4.4.1.2 The crS Operand ...............................................................................................C-10

C.4.5 Simplified Mnemonics that Incorporate the BO Operand.........................................C-11

C.4.5.1 Examples that Eliminate the BO Operand.............................................................C-12

C.4.6 Simplified Mnemonics that Incorporate CR Conditions (Eliminates BO

and Replaces BI with crS).....................................................................................C-15

C.4.6.1 Branch Simplified Mnemonics that Incorporate CR Conditions: Examples.........C-17

C.4.6.2 Branch Simplified Mnemonics that Incorporate CR Conditions: Listings............C-17

C.5 Compare Word Simplified Mnemonics .........................................................................C-20

C.6 Condition Register Logical Simplified Mnemonics ......................................................C-20

C.7 Trap Instructions Simplified Mnemonics ......................................................................C-21

C.8 Simplified Mnemonics for Accessing SPRs..................................................................C-23

C.9 Recommended Simplified Mnemonics..........................................................................C-24

C.9.1 No-Op (nop) ..............................................................................................................C-24

C.9.2 Load Immediate (li) ...................................................................................................C-24

C.9.3 Load Address (la) ......................................................................................................C-24

C.9.4 Move Register (mr)...................................................................................................C-25

C.9.5 Complement Register (not) .......................................................................................C-25

C.9.6 Move to Condition Register (mtcr)...........................................................................C-25

C.10 EIS-Specific Simplified Mnemonics .............................................................................C-26

C.10.1 Integer Select (isel)....................................................................................................C-26

C.10.2 SPE Mnemonics.........................................................................................................C-26

C.11 Comprehensive List of Simplified Mnemonics.............................................................C-26

Appendix D

Opcode Listings

D.1 Instructions (Binary) by Mnemonic................................................................................ D-1

D.2 Instructions (Decimal and Hexadecimal) by Opcode................................................... D-22

D.3 Instructions by Form..................................................................................................... D-35

Appendix E

Revision History

E.1 Major Changes From Revision 0 to Revision 1.............................................................. A-1

Index

Freescale Semiconductor PowerPC e500 Core - Page 20