Freescale Semiconductor PowerPC e500 Core - Page 245

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-43
evmwlusiaaw MU 4:1
evmwlusianw MU 4:1
evmwsmf MU 4:1
evmwsmfa MU 4:1
evmwsmfaa MU 4:1
evmwsmfan MU 4:1
evmwsmi MU 4:1
evmwsmia MU 4:1
evmwsmiaa MU 4:1
evmwsmian MU 4:1
evmwssf MU 4:1
evmwssfa MU 4:1
evmwssfaa MU 4:1
evmwssfan MU 4:1
evmwumi MU 4:1
evmwumia MU 4:1
evmwumiaa MU 4:1
evmwumian MU 4:1
evnand SU1 1
evneg SU1 1
evnor SU1 1
evor SU1 1
evorc SU1 1
evrlw SU1 1
evrlwi SU1 1
evrndw SU1 1
evsel SU1 1
evslw SU1 1
evslwi SU1 1
evsplatfi SU1 1
evsplati SU1 1
evsrwis SU1 1
evsrwiu SU1 1
evsrws SU1 1
evsrwu SU1 1
evsubfsmiaaw MU 4:1
evsubfssiaaw MU 4:1
evsubfumiaaw MU 4:1
Table 4-8. SPE and Embedded Floating-Point APU Instruction Latencies (continued)
Mnemonic Unit Cycles (Latency:Throughput)