Freescale Semiconductor PowerPC e500 Core - Page 244

PowerPC e500 Core Family Reference Manual, Rev. 1
4-42 Freescale Semiconductor
Execution Timing
evmhogumian MU 4:1
evmhosmf MU 4:1
evmhosmfa MU 4:1
evmhosmfaaw MU 4:1
evmhosmfanw MU 4:1
evmhosmi MU 4:1
evmhosmia MU 4:1
evmhosmiaaw MU 4:1
evmhosmianw MU 4:1
evmhossf MU 4:1
evmhossfa MU 4:1
evmhossfaaw MU 4:1
evmhossfanw MU 4:1
evmhossiaaw MU 4:1
evmhossianw MU 4:1
evmhoumi MU 4:1
evmhoumia MU 4:1
evmhoumiaaw MU 4:1
evmhoumianw MU 4:1
evmhousiaaw MU 4:1
evmhousianw MU 4:1
evmra MU 4:1
evmwhsmf MU 4:1
evmwhsmfa MU 4:1
evmwhsmi MU 4:1
evmwhsmia MU 4:1
evmwhssf MU 4:1
evmwhssfa MU 4:1
evmwhumi MU 4:1
evmwhumia MU 4:1
evmwlsmiaaw MU 4:1
evmwlsmianw MU 4:1
evmwlssiaaw MU 4:1
evmwlssianw MU 4:1
evmwlumi MU 4:1
evmwlumia MU 4:1
evmwlumiaaw MU 4:1
evmwlumianw MU 4:1
Table 4-8. SPE and Embedded Floating-Point APU Instruction Latencies (continued)
Mnemonic Unit Cycles (Latency:Throughput)