Freescale Semiconductor PowerPC e500 Core - Page 243

Execution Timing
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 4-41
evfststeq SU1 1
evfststgt SU1 1
evfststlt SU1 1
evmergehi SU1 1
evmergehilo SU1 1
evmergelo SU1 1
evmergelohi SU1 1
evmhegsmfaa MU 4:1
evmhegsmfan MU 4:1
evmhegsmiaa MU 4:1
evmhegsmian MU 4:1
evmhegumiaa MU 4:1
evmhegumian MU 4:1
evmhesmf MU 4:1
evmhesmfa MU 4:1
evmhesmfaaw MU 4:1
evmhesmfanw MU 4:1
evmhesmi MU 4:1
evmhesmia MU 4:1
evmhesmiaaw MU 4:1
evmhesmianw MU 4:1
evmhessf MU 4:1
evmhessfa MU 4:1
evmhessfaaw MU 4:1
evmhessfanw MU 4:1
evmhessiaaw MU 4:1
evmhessianw MU 4:1
evmheumi MU 4:1
evmheumia MU 4:1
evmheumiaaw MU 4:1
evmheumianw MU 4:1
evmheusiaaw MU 4:1
evmheusianw MU 4:1
evmhogsmfaa MU 4:1
evmhogsmfan MU 4:1
evmhogsmiaa MU 4:1
evmhogsmian MU 4:1
evmhogumiaa MU 4:1
Table 4-8. SPE and Embedded Floating-Point APU Instruction Latencies (continued)
Mnemonic Unit Cycles (Latency:Throughput)