Auxiliary Processing Units (APUs)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 10-7
efdabs efdabs
Floating-Point Double-Precision Absolute Value
efdabs rD,rA
rD
0:63
← 0b0 || rA
1:63
The sign bit of rA is cleared and the result is placed into rD.
Exception detection for efdabs is implementation dependent. On the e500v2, the exception is
handled as follows: If rA is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set, and FG and FX are
cleared. If SPEFSCR[FINVE] = 0, the results are the same as for a normalized number. If
SPEFSCR[FINVE] = 1, an interrupt is taken and rD is not updated.
efdadd efdadd
Floating-Point Double-Precision Add
efdadd rD,rA,rB
rD
0:63
← rA
0:63
+
dp
rB
0:63
rA is added to rB and the result is stored in rD. If rA is NaN or infinity, the result is either pmax
(
a
sign
==0), or nmax (a
sign
==1). Otherwise, If rB is NaN or infinity, the result is either pmax
(
b
sign
==0), or nmax (b
sign
==1). Otherwise, if overflow occurs, pmax or nmax (as appropriate) is
stored in rD. If underflow occurs, +0 (for rounding modes RN, RZ, RP) or -0 (for rounding mode
RM) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken and rD is not updated. Otherwise, if overflow or
underflow occurs, SPEFSCR[FOVF] or SPEFSCR[FUNF] is set, and, if the underflow or overflow
exception is enabled, an interrupt is taken. If any of these interrupts is taken, rD is not updated.
If the result is inexact or if an overflow occurs but overflow exceptions are disabled, and no other
interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, a
floating-point round interrupt is taken, rD is updated with the truncated result, and FG and FX are
updated to allow rounding to be performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
0 56 101115162021 31
000100 rD rA 0 00000 1011100100
0 56 101115162021 31
000100 rD rA rB 0 1011100000
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