PowerPC e500 Core Family Reference Manual, Rev. 1
10-8 Freescale Semiconductor
Auxiliary Processing Units (APUs)
efdcfs efdcfs
Floating-Point Double-Precision Convert from Single-Precision
efdcfs rD,rB
FP32format f;
FP64format result;
f
← rB
32:63
if (f
exp
= 0) & (f
frac
= 0)) then
result
← f
sign
||
63
0 // signed zero value
else if Isa32NaNorInfinity(f) | Isa32Denorm(f) then
SPEFSCR
FINV
← 1
result
← f
sign
|| 0b11111111110 ||
52
1 // max value
else if Isa32Denorm(f) then
SPEFSCR
FINV
← 1
result
← f
sign
||
63
0
else
result
sign
← f
sign
result
exp
← f
exp
- 127 + 1023
result
frac
← f
frac
||
29
0
rD
0:63
= result
The single-precision floating-point value in the low element of rB is converted to a
double-precision floating-point value and the result is placed into rD. The rounding mode is not
used since this conversion is always exact.
Exceptions:
If the low element of rB is Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated.
FG and FX are always cleared.
0 56 101115162021 31
000100 rD 00000 rB 0 1011101111
To Next Page
Loading...
