Auxiliary Processing Units (APUs)
PowerPC e500 Core Family Reference Manual, Rev. 1
Freescale Semiconductor 10-15
efddiv efddiv
Floating-Point Double-Precision Divide
efddiv rD,rA,rB
rD
0:63
← rA
0:63
÷
dp
rB
0:63
rA is divided by rB and the result is stored in rD. If rB is a NaN or infinity, the result is a properly
signed zero. Otherwise, if rB is a zero (or a denormalized number optionally transformed to zero
by the implementation), or if rA is either NaN or infinity, the result is either pmax (
a
sign
==b
sign
),
or nmax (
a
sign
!=b
sign
). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is stored
in rD. If an underflow occurs, +0 or -0 (as appropriate) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, or if both rA and rB are +/-0,
SPEFSCR[FINV] is set. If SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated.
Otherwise, if the content of rB is +/-0 and the content of rA is a finite normalized non-zero
number, SPEFSCR[FDBZ] is set. If floating-point divide by zero Exceptions are enabled, an
interrupt is then taken. Otherwise, if an overflow occurs, SPEFSCR[FOVF] is set, or if an
underflow occurs, SPEFSCR[FUNF] is set. If either underflow or overflow exceptions are enabled
and the corresponding bit is set, an interrupt is taken. If any of these interrupts are taken, rD is not
updated.
If the result of this instruction is inexact or if an overflow occurs but overflow exceptions are
disabled, and no other interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point inexact
exception is enabled, an interrupt is taken using the floating-point round interrupt vector. In this
case, rD is updated with the truncated result, FG and FX are updated to allow rounding to be
performed in the interrupt handler.
FG and FX are cleared if an overflow, underflow, divide by zero, or invalid operation/input error
is signaled, regardless of enabled exceptions.
0 56 101115162021 31
000100 rD rA rB 0 1011101000
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