PowerPC e500 Core Family Reference Manual, Rev. 1
10-14 Freescale Semiconductor
Auxiliary Processing Units (APUs)
efdctui efdctui
Convert Floating-Point Double-Precision to Unsigned Integer
efdctui rD,rB
rD
32:63
← CnvtFP64ToI32Sat(rB
0:63
, UNSIGN, ROUND, I
The double-precision floating-point value in rB is converted to an unsigned integer using the
current rounding mode and the result is saturated if it cannot be represented in a 32-bit integer.
NaNs are converted as though they were zero.
Exceptions:
If rB contents are Infinity, Denorm, or NaN or if an overflow occurs, SPEFSCR[FINV] is set, and
FG and FX are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken and rD is not updated.
If conversion is inexact, inexact status is signalled and SPEFSCR[FINXS] is set. If the
floating-point inexact exception is enabled, a floating-point round interrupt is taken, rD is updated
with the truncated result, and FG and FX are updated so the handler can perform rounding.
efdctuiz efdctuiz
Convert Floating-Point Double-Precision to Unsigned Integer with Round toward Zero
efdctuiz rD,rB
rD
32:63
← CnvtFP64ToI32Sat(rB
0:63
, UNSIGN, TRUNC, I)
The double-precision floating-point value in rB is converted to an unsigned integer using the
rounding mode Round toward Zero and the result is saturated if it cannot be represented in a 32-bit
integer. NaNs are converted as though they were zero.
Exceptions:
If rB contents are Infinity, Denorm, or NaN or if an overflow occurs, SPEFSCR[FINV] is set and
FG and FX are cleared. If SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated.
If conversion is inexact, inexact status is signalled and SPEFSCR[FINXS] is set. If the
floating-point inexact exception is enabled, a floating-point round interrupt is taken, rD is updated
with the truncated result, and FG and FX are updated to allow the handler to perform rounding .
0 56 101115162021 31
000100 rD 00000 rB 0 1011110100
0 56 101115162021 31
000100 rD 00000 rB 0 1011111000
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