PowerPC e500 Core Family Reference Manual, Rev. 1
10-18 Freescale Semiconductor
Auxiliary Processing Units (APUs)
efdsub efdsub
Floating-Point Double-Precision Subtract
efdsub rD,rA,rB
rD
0:63
← rA
0:63
-
dp
rB
0:63
rB is subtracted from rA and the result is stored in rD. If rA is NaN or infinity, the result is either
pmax (
a
sign
==0), or nmax (a
sign
==1). Otherwise, If rB is NaN or infinity, the result is either nmax
(
b
sign
==0), or pmax (b
sign
==1). Otherwise, if an overflow occurs, pmax or nmax (as appropriate) is
stored in rD. If an underflow occurs, +0 (for rounding modes RN, RZ, RP) or -0 (for rounding
mode RM) is stored in rD.
Exceptions:
If the contents of rA or rB are Infinity, Denorm, or NaN, SPEFSCR[FINV] is set. If
SPEFSCR[FINVE] is set, an interrupt is taken, and rD is not updated. Otherwise, if an overflow
occurs, SPEFSCR[FOVF] is set, or if an underflow occurs, SPEFSCR[FUNF] is set. If either
underflow or overflow exceptions are enabled and the corresponding bit is set, an interrupt is taken.
If any of these interrupts are taken, rD is not updated.
If the result is inexact or if overflow occurs but overflow exceptions are disabled, and no other
interrupt is taken, SPEFSCR[FINXS] is set. If the floating-point inexact exception is enabled, a
floating-point round interrupt is taken, rD is updated with the truncated result, and FG and FX are
updated to allow the interrupt handler to perform rounding.
FG and FX are cleared if an overflow, underflow, or invalid operation/input error is signaled,
regardless of enabled exceptions.
0 56 101115162021 31
000100 rD rA rB 0 1011100001
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