Élan™SC520 Microcontroller User’s Manual 6-1
CHAPTER
6
RESET GENERATION
6.1 OVERVIEW
Reset features of the ÉlanSC520 microcontroller include:
■ ÉlanSC520 microcontroller system reset generation via PWRGOOD pin, software
writes, watchdog timer, and AMDebug system reset
■ ÉlanSC520 microcontroller system reset with SDRAM interface contents maintained
(called
programmable reset
)
■ Hard CPU reset generation via system reset
■ Soft CPU reset generation via software writes and detection of the CPU special cycle
type “shutdown”
■ GP bus reset generation via system reset and software writes
■ PCI bus reset generation via system reset and software writes. See Chapter 9, “PCI
Bus Host Bridge”
■ Reset sources can be determined by software
■ Latches system-configuration data presented on the shared CFG3–CFG0 pins and static
system board information presented on the shared RSTLD7–RSTLD0 pins at the
assertion of the PWRGOOD pin. See Chapter 12, “ROM/Flash Controller”, for
information in the CFGx pins.
■ System Control Processor (SCP) A20 gate and reset CPU command emulation
■ Control bit to enable AMDebug mode after the CPU has been reset
6.2 BLOCK DIAGRAM
Figure 6-1 shows a block diagram of the reset controller.
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