Élan™SC520 Microcontroller User’s Manual 10-1
CHAPTER
10
SDRAM CONTROLLER
10.1 OVERVIEW
The ÉlanSC520 microcontroller includes an integrated SDRAM controller.
Features include:
■ SDRAM (synchronous DRAM) support
■ 3.3-V DC 66-MHz SDRAM or faster (16 Mbit through 256 Mbit)
■ Achieves 3-1-1-1 read bursts on SDRAM (page hit for all device speed grades with
CAS
latency (C
L
) = 2)
■ Support for up to four banks, each bank independently programmed for size and
symmetry (symmetric and asymmetric SDRAMs)
■ Up to 256 Mbytes of SDRAM
■ Optional SDRAM refresh during reset
■ SDRAM auto refresh
■ Error Correction Code (ECC) support (single-bit correct/multi-bit detect)
■ SDRAM write buffering that supports write-merging, write-collapsing, and read-merging
■ Read buffer with read-ahead feature for SDRAM read prefetching
■ Read-around-write support that gives read priority over posted writes when the write
buffer is enabled
10.2 BLOCK DIAGRAM
The SDRAM controller and its interface to the system SDRAM, along with the write buffer
and the read buffer, are shown in Figure 10-1. (The write buffer and read buffer are
described in Chapter 11.) Figure 10-2 shows a more detailed block diagram of the SDRAM
controller subsystem.
10.3 SYSTEM DESIGN
The SDRAM controller of the ÉlanSC520 microcontroller supports SDRAM devices only.
Figure 10-3 illustrates the connection of the SDRAM signals from the ÉlanSC520
microcontroller to the SDRAM banks.
Although the data bus width is only 32-bits in the ÉlanSC520 microcontroller, 64-bit (168-
pin DIMMs) memory modules can be used. Each 168-pin DIMM can be used as a pair of
banks. By appropriately connecting the SCS3
–SCS0 signals to the SDRAM DIMM module,
168-pin modules can be used in an ÉlanSC520 microcontroller system.
Figure 10-4 shows an example configuration of a 168-pin SDRAM DIMM used as two banks.
For the DIMM in this example, 8-bit devices are used. A DIMM configured for ECC is not
shown.
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