System Address Mapping
4-8 Élan™SC520 Microcontroller User’s Manual
4.3.3.1 SDRAM Space
SDRAM space in an ÉlanSC520 microcontroller system defaults to a linear region starting
at the lowest 32-bit memory address (00000000h) and ending at the top of SDRAM, which
is defined by the amount of SDRAM populated in the system and programmed in the
SDRAM controller’s configuration registers.
The maximum amount of SDRAM supported in an ÉlanSC520 microcontroller system is
256 Mbytes, in various configurations between one and four physical banks. Once the
SDRAM configuration registers are programmed and the individual banks are enabled,
SDRAM is immediately accessible.
The ÉlanSC520 microcontroller allows special attributes to be applied to any region within
SDRAM space. These attributes are not required for normal operation, however some
applications can benefit from their use. Programming PAR registers for SDRAM access is
required
only
if special attributes must be applied to specific SDRAM regions, as described
below. There are three attributes that can be applied to any SDRAM region:
■ Noncacheable regions
■ Write-protected regions
■ Code execution control
In a typical system configuration, an external PCI bus master has full access to the entire
SDRAM region. The address decoding logic in the ÉlanSC520 microcontroller’s PCI host
bridge automatically claims cycles to this address space on the PCI bus generated by
external PCI bus masters and causes them to be directed to SDRAM. PCI bus master
cycles that are forwarded to the memory controller always result in an SDRAM cycle, even
if a PAR register has been programmed to redirect the address to the GP bus or ROM.
Also, if a PCI bus master generates a memory write cycle that is forwarded to the memory
controller and a PAR has been programmed to write-protect the region, an SDRAM write
cycle will occur with the SDQM signals inactive, the data will be discarded, and the data
written into the PCI bridge FIFOs will be purged. The ÉlanSC520 microcontroller can be
programmed to generate an interrupt in this case to notify the CPU of such write protection
violations, and that a PCI bus master caused the violations. Any data written to the write
buffer prior to enabling write-protection will be successfully written to SDRAM.
4.3.3.2 ROM/Flash Space
The ÉlanSC520 microcontroller supports three separate address regions for ROM/Flash,
which are selected by the PAR registers. The BOOTCS
ROM chip select must be used for
the boot device and defaults to a 64-Kbyte linear region at the top of the 4-Gbyte CPU
space. During the boot process, the ROM code can configure PAR registers to enable the
entire BOOTCS
ROM space and redirect it to the desired region. The default 64-Kbyte
region is always enabled, however. The PAR register accepts separate TARGET values
for each of the three ROM chip select regions (BOOTCS
, ROMCS1, and ROMCS2). ROM
space is accessible by the CPU only, regardless of PAR register programming.
ROM space is normally cacheable and writes to these regions are allowed (this is useful
for Flash devices). However, PAR registers can also be used to enable specific attributes,
such as defining noncacheability and write-protected regions.
The ÉlanSC520 microcontroller supports multiple data widths in the ROM array, as well as
programmable timing. These characteristics are configured independently of the address
space in the ÉlanSC520 microcontroller. See Chapter 12, “ROM/Flash Controller”, for a
description of these features and instructions for configuring the ROM chip select timing
and data widths.
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