Architectural Overview
1-2 Élan™SC520 Microcontroller User’s Manual
– Parallel debug port for high-speed data exchange during in-circuit emulation
■ General-purpose (GP) bus with programmable timing for 8- and 16-bit devices provides
good performance at very low cost.
■ ROM/Flash controller for 8-, 16-, and 32-bit devices
■ Enhanced PC/AT-compatible peripherals provide improved performance.
– Enhanced programmable interrupt controller (PIC) prioritizes 22 interrupt levels (up
to 15 external sources) with flexible routing.
– Enhanced DMA controller includes double buffer chaining, extended address and
transfer counts, and flexible channel routing.
– Two 16550-compatible UARTs operate at baud rates up to 1.15 Mbit/s with optional
DMA interface.
■ Standard PC/AT-compatible peripherals
– Programmable interval timer (PIT)
– Real-time clock (RTC) with battery backup capability and 114 bytes of RAM
■ Additional integrated peripherals
– Three general-purpose 16-bit timers provide flexible cascading for 32-bit operation.
– Watchdog timer guards against runaway software.
– Software timer
– Synchronous serial interface (SSI) offers full-duplex or half-duplex operation.
– Flexible address decoding for programmable memory and I/O mapping and system
addressing configuration
■ 32 programmable input/output (PIO) pins
■ Native support for pSOS, QNX, RTXC, VxWorks, and Windows
®
CE operating systems
■ Industry-standard BIOS support
1.2 BLOCK DIAGRAM
Figure 1-1 on page 1-3 illustrates the integrated Am5
x
86 CPU, bus structure, and on-chip
peripherals of the ÉlanSC520 microcontroller. Three primary interfaces are provided:
■ A high-performance, 66-MHz 32-bit synchronous DRAM (SDRAM) interface of up to
256 Mbytes is used for Am5
x
86 CPU code execution, as well as buffer storage of external
PCI bus masters and GP bus DMA initiators. A high-performance ROM/Flash interface
can also be connected to the SDRAM interface.
■ An industry-standard, 32-bit PCI bus is provided for high bandwidth I/O peripherals such
as local area network controllers, synchronous communications controllers, and disk
storage controllers.
■ A simple 8/16-bit, 33-MHz general-purpose bus (GP bus) provides a glueless connection
to lower bandwidth peripherals, and NVRAM, SRAM, ROM, or custom ASICs; supports
dynamic bus sizing and compatibility with many common ISA devices.
These three buses listed above are provided in all operating modes of the ÉlanSC520
microcontroller.
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