AMD Elan SC520 - CPU Latency; High-Priority Queue Latency; Low-Priority Queue Latency; Nonconcurrent Arbitration Mode Latency

System Arbitration
Élan™SC520 Microcontroller User’s Manual 8-21
8.4.7.2 High-Priority Queue Latency
The maximum latency for a master in the high-priority queue is the sum of:
■ Master latency timer of other master in high-priority queue—This time can be decreased
by decreasing the master latency timer of the other master in the high-priority queue, or
this time can be eliminated by programming only one master in the high-priority queue.
■ Longest master latency timer of all masters in the low-priority queue—This can be
decreased by decreasing the master latency timer of all masters in the low-priority queue.
■ 3 * (Am5
x
86 CPU maximum transaction time)
8.4.7.3 Low-Priority Queue Latency
The maximum latency for a master in the low-priority queue (note that after a low-priority
master has completed a transaction, every PCI master will be granted the bus before the
low-priority master will be granted the bus again) is the sum of:
■ Number of external masters * (Am5
x
86 CPU maximum transaction time)—The Am5
x
86
CPU maximum transaction time is multiplied by the number of external masters, because
the Am5
x
86 CPU is granted the bus after every external PCI transaction if the Am5
x
86
CPU relative priority is configured for one external PCI master cycle. This can be
decreased by decreasing the Am5
x
86 CPU relative priority (configure the relative priority
to allow more external PCI cycles for every Am5
x
86 CPU PCI cycle).
■ Number of masters in the low-priority queue * (master latency timers of all masters in
the high-priority queue)—The master latency timers of all masters in the high-priority
queue is multiplied by the number of masters in the low-priority queue, because the
high-priority masters are granted the bus after each low-priority master grant. This time
can be decreased by decreasing the number of masters in the high-priority queue or by
decreasing the master latency timers of the masters in the high-priority queue.
■ Master latency timers of all masters in the low-priority queue—This time can be
decreased by decreasing the master latency timers of the masters in the low-priority
queue.
8.4.7.4 CPU Latency
The maximum latency for the Am5
x
86 CPU is:
■ 3 * (longest master latency timer of all external masters)—The master latency timer is
multiplied by 3 because the worst case is when the Am5
x
86 CPU relative priority is
configured for three external PCI master cycles for every Am5
x
86 CPU PCI cycle. This
time can be decreased by decreasing the master latency timers of external masters or
by increasing the Am5
x
86 CPU relative priority.
8.4.7.5 Nonconcurrent Arbitration Mode Latency
Operating in nonconcurrent arbitration mode adds to the PCI bus latency. In nonconcurrent
arbitration mode, all PCI masters must be granted the CPU bus in addition to the PCI bus
before a transaction can proceed. The time associated with being granted the CPU bus
adds to each PCI master’s latency.
The maximum latency is:
(time for the longest Am5
x
86 CPU transfer) + (time for the longest GP-DMA transfer)
The longest Am5
x
86 CPU transfer is one cache line, and the longest GP-DMA transfer is
programmable. This additional latency is added to the latency of each external PCI master
as calculated in the high-priority and low-priority queues. This latency is incurred for all PCI