AMD Elan SC520 - Addressing GP-DMA Channels; Addressing in Normal GP-DMA Mode; Enhanced GP-DMA Mode

GP Bus DMA Controller
Élan™SC520 Microcontroller User’s Manual 14-11
14.5.2.2 Enhanced GP-DMA Mode
Only channels 3, 5, 6, and 7 support enhanced GP-DMA mode. In enhanced GP-DMA
mode:
■ Each of these four channels can be configured to be either 8-bit or 16-bit channel. The
other channels (0, 1, and 2) can still be used as normal 8-bit channels in conjunction
with the enhanced GP-DMA mode channels.
■ The transfer count registers are increased to 24 bits in size, providing the capability of
transferring up to 32 Mbytes of data.
■ The address adder is increased to 28 bits in size, eliminating the limitation of transferring
within the 64 Kbytes boundaries (128 Kbytes for 16-bit devices) in normal GP-DMA
mode.
This mode also offers the capability of chaining two noncontiguous memory buffers during
DMA transfers, as described in “Buffer Chaining” on page 14-15.
14.5.3 Addressing GP-DMA Channels
14.5.3.1 Addressing In Normal GP-DMA Mode
GP-DMA Channel 4 is used to cascade channels 0–3 from the slave core through the
master core to the CPU and is not available for data transfer. For proper operation, software
must ensure that this setting is always configured for cascading only via the TRNMOD field
in the Master DMA Channel 4–7 Mode (MSTDMAMODE) register (Port 00D6h).
14.5.3.1.1 8-Bit Transfers
Channels 0–3 support 8-bit data transfers between 8-bit I/O devices and system SDRAM.
8-bit GP-DMA can access any location within the system address space; however, the
address adder is only 16 bits wide, so 8-bit GP-DMA requests cannot cross 64-Kbyte
physical page boundaries. As shown in Table 14-6, during an 8-bit GP-DMA transfer:
■ The Slave DMA Channel x Memory Address (GPDMAxMAR) registers provide address
bits 15–0.
■ The Slave DMA Channel x Page (GPDMAxPG) registers provide address bits 23–16.
■ The GP-DMA Channel x Extended Page (GPDMAEXTPGx) registers provide bits
27–24 of the system memory address.
14.5.3.1.2 16-Bit Transfers
Channels 5–7 support 16-bit data transfers between 16-bit I/O devices and system SDRAM.
16-bit GP-DMA can access any even (word-aligned) location within the system address
space; however, the address adder is only 16 bits wide, so 16-bit GP-DMA requests cannot
cross 128-Kbyte physical page boundaries. During a 16-bit GP-DMA transfers:
■ A0 is forced to 0.
■ The Master DMA Channel x Memory Address (GPDMAxMAR) registers provide address
bits 16–1.
■ The Master DMA Channel x Page (GPDMAxPG) registers provide address bits 23–17.
■ The GP-DMA Channel x Extended Page (GPDMAEXTPGx) registers provide bits
27–24 of the system memory address.