Programmable Interrupt Controller
15-8 Élan™SC520 Microcontroller User’s Manual
4. The CPU reads the interrupt vector and services the interrupt corresponding to the vector
read during the acknowledgment.
5. Before further interrupts for the same priority level can be serviced, an EOI (end-of-
interrupt must be issued to the PIC to reset the In-Service (xISR) register bit of the
currently active interrupt. This can be done in one of two ways.
– In automatic EOI (AEOI) mode, the In-Service (xISR) register bit is reset at the end
of the acknowledgement cycle from the CPU. It must be understood that AEOI mode
does not support polling and can only be used in a master configuration and not a slave.
– When AEOI is disabled, the interrupt handler must clear the In-Service (xISR) register
bit by issuing a EOI command at the end of the interrupt service routine.
For an interrupt request coming from either one of the slave controllers, the slave controller
generates an interrupt to the Master controller and asserts its corresponding Interrupt
Request (xIR) register bit at the Master controller. The Master controller first determines if
there is a higher priority interrupt that is currently being serviced. If there is not, it requests
an interrupt from the CPU, as described in step 2. Otherwise, the higher priority interrupt
service routine continues uninterrupted until another interrupt request is received from the
PIC.
There are two ways in which an interrupt request from a slave controller differs from the
interrupt sequence mentioned above. Steps 3–5 are similar in this case, but because the
Interrupt Request (xIR) register bit set by the slave output is the highest priority interrupt,
the Master controller now commands the slave controller to supply the interrupt vector to
the CPU.
The other difference is that two EOIs are required: one to the Master controller to reset its
highest priority In-Service (xISR) register bit (set by the interrupt request) and the other to
the slave to reset its highest priority In-Service (xISR) register bit. The order of these two
EOIs does not matter.
15.5.2 Interrupt Sources
The interrupt sources in the ÉlanSC520 microcontroller can be divided into four distinct
categories:
■ Externally-generated hardware interrupts from interrupt input pins
■ Internally-generated hardware interrupts from peripherals
■ Internally-generated hardware interrupts from interrupt trigger bits
■ Software interrupts (generated with the INT instructions)
This section discusses all of these except software interrupts. Note that the first two
hardware interrupt sources listed above can be mapped to the Am5
x
86 CPU’s NMI interrupt
input. NMI is discussed in “Non-Maskable Interrupts and Routing” on page 15-14. Software
interrupts work in the standard x86 fashion and are not discussed in this manual.
15.5.2.1 Hardware-Generated Interrupts
In the ÉlanSC520 microcontroller, there are 57 hardware interrupt sources:
■ 23 can come from control bits in the Software Interrupt 16–1 Control (SWINT16_1)
register (MMCR offset D08h) and the Software Interrupt 22–17/NMI Control
(SWINT22_17) register (MMCR offset D0Ah).
■ 15 can come from the 15 external interrupt pins (GPIRQ10–GPIRQ0 and INTA–INTD)
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