System Arbitration
8-18 Élan™SC520 Microcontroller User’s Manual
8.4.4.6 Nonconcurrent Mode Arbitration
Figure 8-11 shows external PCI master arbitration in nonconcurrent mode. In
nonconcurrent arbitration mode, both the CPU bus and the PCI bus are granted to the PCI
master, regardless of the destination of the PCI transaction.
Figure 8-11 Nonconcurrent Mode Arbitration
Notes:
The diagram includes the following internal signals:
• hb_req: PCI host bridge requesting the Am5
x
86 CPU bus.
• hb_gnt: PCI host bridge has been granted Am5
x
86 CPU bus.
The following sequence annotates the nonconcurrent mode arbitration cycle shown in
Figure 8-11.
■ Clock #1: An external PCI master requests the PCI bus.
■ Clock #2: The PCI bus arbiter samples an external PCI request asserted and asserts
the host bridge request to the CPU bus arbiter. The external PCI master GNT0
cannot
be asserted until the host bridge is granted the CPU bus. If the system arbiter were
operating in concurrent arbitration mode, the external PCI master GNT0
could be
asserted in clock #2 because the PCI bus and the CPU bus would be operating
independently.
■ Clock #5: The CPU bus arbiter has determined the host bridge will be granted the CPU
bus and asserts hb_gnt to the host bridge. The assertion of hb_gnt could be delayed if
a higher priority master was requesting the CPU bus.
■ Clock #6: The PCI bus arbiter detects the host bridge has been granted the CPU bus
and asserts GNT0
to the external PCI master.
■ Clock #7: The CPU bus arbiter rearbitrates and determines another CPU bus master
will be granted the bus and deasserts hb_gnt to the host bridge. The host bridge will
1 2 3 4 5 6 7 8 9 10 11 12
CLKPCIIN
REQ0
GNT0
hb_req
hb_gnt
FRAME
DEVSEL
IRDY
TRDY
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