AMD Elan SC520 - Bus Cycles; If JTAG_TMS Is Low; The Controller Remains in this State as Long as JTAG_TMS Is Low. When JTAG_TMS Goes; The Scanning Process. if JTAG_TMS Is Held Low and a Rising Edge Is Applied to JTAG_TCK

Boundary Scan Test Interface
25-18 Élan™SC520 Microcontroller User’s Manual
25.4.3.1.13 Exit1-IR State
This is a temporary state. In this state, if JTAG_TMS is held High, a rising edge applied to
JTAG_TCK causes the controller to enter the Update-IR state, which terminates the
scanning process. If JTAG_TMS is held Low and a rising edge is applied to JTAG_TCK,
the controller enters the Pause-IR state.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
25.4.3.1.14 Pause-IR State
The pause state allows the test controller to temporarily halt the shifting of data through
the Instruction register.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
The controller remains in this state as long as JTAG_TMS is Low. When JTAG_TMS goes
High and a rising edge is applied to JTAG_TCK, the controller moves to the Exit2-IR state.
25.4.3.1.15 Exit2-IR State
This is a temporary state. While in this state, if JTAG_TMS is held High, a rising edge
applied to JTAG_TCK causes the controller to enter the Update-IR state, which terminates
the scanning process. If JTAG_TMS is held Low and a rising edge is applied to JTAG_TCK,
the controller enters the Shift-IR state.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
25.4.3.1.16 Update-IR State
The instruction shifted into the Instruction register is latched onto the parallel output from
the shift-register path on the falling edge of JTAG_TCK. When the new instruction has been
latched, it becomes the current instruction.
Test data registers selected by the current instruction retain their previous value.
When the TAP controller is in this state and a rising edge is applied to JTAG_TCK, the
controller enters the Select-DR State if JTAG_TMS is held High or Run-Test Idle state if
JTAG_TMS is held Low.
25.4.4 Bus Cycles
Figure 25-5 and Figure 25-6 give the bus cycles information of the test logic operation in
data scan mode and instruction scan mode, respectively.