AMD Elan SC520 - Figure 11-6 Bus Thrashing with Write Buffer Disabled and Enabled

Write Buffer and Read Buffer
11-14 Élan™SC520 Microcontroller User’s Manual
Since the write buffer supports data read-merging, data coherency overhead is kept to a
minimum. The write buffer’s read-merging capability is possible due to the write buffer’s
ability to snoop its own contents during read and write cycles. In the special case of a read
to an address contained in the write buffer, the overhead associated with flushing the entire
contents of the write buffer to maintain data coherency is eliminated. In this case, as data
is returned from SDRAM during the read cycle, more current data in the write buffer is
merged into the data stream, replacing older data bytes being returned from SDRAM. This
greatly enhances the read-around-write behavior by eliminating the overhead associated
with flushing the write buffer to maintain coherency.
The maximum write buffer performance is seen during individual contiguous byte writes to
SDRAM. For example, suppose the GP-DMA was performing a 64-byte block transfer from
an 8-bit device to SDRAM. Without the write buffer, this would require 64 individual byte-
wide transfers to SDRAM. Because of the write buffer’s write data-merging capability, each
contiguous byte could be merged to form only 16 doubleword transfers to SDRAM. This
would reduce the total number of SDRAM writes cycles from 64 to 16 in this example.
The write buffer also improves memory system performance during heavy SDRAM write
data thrashing between multiple masters. Since the write buffer provides zero wait state
posting of write data, the SDRAM interface is freed up earlier to service another master’s
request. While the next master is arbitrating for SDRAM, the write buffer can concurrently
be writing back the data posted by previous masters. Therefore, during heavy SDRAM write
thrashing periods by multiple masters, the write buffer can help to hide the arbitration
overhead. This is shown in Figure 11-6.
Figure 11-6 Bus Thrashing with Write Buffer Disabled and Enabled
The maximum benefit of the read buffer’s read-ahead feature is provided during consecutive
prefetch hits. This will most likely occur during long master burst tenure or consecutive
bursts by the same master. For example, suppose a PCI master requests a 256-byte (64-
doubleword) read transfer from SDRAM. Since the read buffer prefetches a cache line
forward and PCI burst transfers are linear and forward in nature, consecutive requests can
be satisfied by data prefetched by the read-ahead feature.
System with Write Buffer Disabled
CPU PCI GP Bus CPUArb
Arb
CPU PCI CPUArb Arb
System with Write Buffer Enabled
SDRAM access
SDRAM access SDRAM access SDRAM accessArb
SDRAM access
Arb
SDRAM access
Arb
SDRAM access SDRAM access
Arb Arb
Arb Arb
Arb
GP Bus