AMD Elan SC520 - Programmable Bus Interface Timing; Timing Requirements

General-Purpose Bus Controller
Élan™SC520 Microcontroller User’s Manual 13-7
The GP bus also provides an echo mode that is useful for debugging. If GP bus echo mode
enabled, the internal GP bus cycle is echoed out on the external pins to enable visibility of
internal cycles. Accesses to internal peripherals that are “echoed” out utilize the
programmed timing set to ensure that there is no timing conflict with other external
peripherals. Note that enabling echo mode does not affect the operation of GP-DMA
accesses or GP bus external accesses.
13.5.1 Programmable Bus Interface Timing
The bus interface timing can be programmed for the following signals:
■ Chip selects GPCS7–GPCS0
■ Read strobes GPIORD and GPMEMRD
■ Write strobes GPIOWR and GPMEMWR
■ Address latch enable GPALE
For each of these signals, the following parameters can be programmed:
■ Offset from beginning of the bus cycle
■ Pulse width from end of the offset
■ Chip select recovery time
Figure 13-4 shows the shows the relationships between the various adjustable GP bus
timing parameters. The actual time can be calculated with the following formula:
(REG_VAL + 1) * T
CLK
where:
REG_VAL = register content value
T
CLK
= internal clock period
The minimum offset, pulse width and recovery time is 30 ns (for a 33.333-MHz crystal),
resulting in a minimum bus cycle time of 90 ns. Since the offset, pulse width, and recovery
parameters are each 8-bit values (maximum 255), the longest bus cycle in this case is 23
µs (2
(8 bits)
* 30 ns * 3 registers).
13.5.1.1 Timing Requirements
The programmed timing of the chip select determines the overall length of the GP bus
cycle. Therefore, the timing parameters for the chip select must be appropriately
programmed. This is required even if the external device does not require a connection to
the GPCSx
pin.
■ To ensure that the command strobes (read or write) assert for the programmed time,
the programmed Offset + Pulse Width + Recovery of the chip select must be programmed
to be
longer than the programmed Offset + Pulse Width of the command strobes.
■ Similarly, to ensure that GPALE is asserted for the programmed time, the programmed
Offset + Pulse Width + Recovery of the chip select must be programmed to be
longer
than the programmed Offset + Pulse Width of the GPALE.