Reset Generation
Élan™SC520 Microcontroller User’s Manual 6-7
6.5.3 Soft CPU Reset
A soft CPU reset is differentiated from a hard CPU reset in that soft CPU reset does not
affect the CPU’s cache state. See “Initialization” on page 7-5 for more information about
the differences between hard and soft CPU reset.
A soft CPU reset does not reset the ÉlanSC520 microcontroller’s internal register bits, with
the exception of the NMI_ENB bit in the Interrupt Control (PICICR) register (MMCR offset
D00h). A soft CPU reset does not assert the GPRESET or RST
pins. For a soft CPU reset,
the CPU’s internal sreset signal is asserted for 16 clock cycles.
There are four ways a soft CPU reset is generated on the ÉlanSC520 microcontroller:
■ A software write to the CPU_RST bit of System Control Port A (SYSCTLA) register (Port
0092h)—Writing a 1 to this bit generates a soft reset event. Following this reset, the
CPU_RST bit remains set until software clears it. To perform a successive reset of the
CPU by software, this bit must be cleared to 0 and then written back to 1. This feature
can be used by software as an indication that the System Control Port A (SYSCTLA)
register was used to generate the reset.
■ SCP Reset CPU command—A soft reset event is asserted when the CPU issues the
standard command write of FEh to the SCP Command Port (SCPCMD) register (Port
0064h).
■ Triple bus fault—A soft reset event is asserted in response to a CPU shutdown cycle
due to a triple bus fault.
■ Entering AMDebug mode—A soft reset event is also asserted in response to a soft reset
command from the AMDebug utility. If the ICE_ON_RST bit in the Reset Configuration
(RESCFG) register (MMCR offset D72h) is set to a 1, the AMDebug utility enters into
AMDebug mode after a soft CPU reset.
6.5.4 GP Bus Reset
GP bus reset can be generated via a system reset or a software write. Writing a 1 to the
GP_RST bit in the Reset Configuration (RESCFG) register (MMCR offset D72h) asserts
the GPRESET pin. Clearing this bit to 0 deasserts the GPRESET pin.
6.5.5 PCI Reset
The PCI reset signal, RST, is generated via a system reset or software writes. Writing a 1
to the PCI_RST bit in the Host Bridge Control (HBCTL) register (MMCR offset 60h) asserts
the PCI RST
pin. Clearing this bit to 0 deasserts the PCI RST pin.
6.5.6 RTC Reset
RTC reset occurs anytime the BBATSEN input is sampled below 2.0 V during a power-on
reset or during a system reset where the reset source was PWRGOOD. RTC Status D
(RTCSTAD) register (RTC index 0Dh) includes a status bit that indicates the validity of the
contents of the RAM, time registers, and the calendar. The RTC_VRT bit is set based on
the assertion of the internal RTC reset.
Note that this RTC reset may or may not occur when a system reset occurs, depending on
the reset source and the state of BBATSEN. BBATSEN also provides a reset signal for the
RTC when an RTC backup battery is applied for the first time.
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