Élan™SC520 Microcontroller User’s Manual 13-1
CHAPTER
13
GENERAL-PURPOSE BUS
CONTROLLER
13.1 OVERVIEW
The ÉlanSC520 microcontroller includes an integrated general-purpose bus (GP bus)
controller. The GP bus is an internal and external bus that connects 8-bit or 16-bit peripheral
devices and memory to the ÉlanSC520 microcontroller without glue logic.The GP bus
operates at 33 MHz, which provides good performance at very low interface cost.
Features of the general-purpose bus controller include:
■ Up to eight external chip selects (GPCS7–GPCS0)
■ Supports 8- and 16-bit I/O and memory cycles
■ Programmable bus interface timing
■ Dynamic bus sizing using GPIOCS16 and GPMEMCS16
■ Dynamic wait state support for external devices using GPRDY
■ Up to 64 Mbytes of memory address space per chip select
■ Supports 8- and 16-bit DMA initiators
13.2 BLOCK DIAGRAM
Figure 13-1 shows the block diagram of the GP bus controller.
13.3 SYSTEM DESIGN
Table 13-1 shows GP bus signals shared with other interfaces on the ÉlanSC520
microcontroller. The pinstrap functions associated with the GPA25–GPA14 pins are
sampled only as a result of PWRGOOD assertion and do not affect the GP bus functions
of these pins, so they are not shown in this table. When enabled, the multiplexed signals
shown in Table 13-1 either disable or alter any other function that uses the same pin.
A ROM device’s data bus can be connected to either the GP bus data bus or the SDRAM
data bus. However, the addresses for ROM devices are always provided via the GP bus,
independently of whether the data pins of the ROM are connected to the GP bus or SDRAM
bus. In either case, the ROM access shares GPA25–GPA0 with the GP bus.
For additional system diagrams using the GP bus, see “Interfacing with a Super I/O
Controller” on page 13-13 and “Interfacing with an AMD Enhanced Serial Communications
Controller (8 MHz)” on page 13-14.
See the
Élan™SC520 Microcontroller Data Sheet
, order #22003, for timing tables and
additional timing diagrams.
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