EasyManua.ls Logo

AMD Elan SC520 - Chapter 1 Architectural Overview; Élansc520 Microcontroller; Distinctive Characteristics

AMD Elan SC520
444 pages
Print Icon
To Next Page IconTo Next Page
To Next Page IconTo Next Page
To Previous Page IconTo Previous Page
To Previous Page IconTo Previous Page
Loading...
Élan™SC520 Microcontroller User’s Manual 1-1
CHAPTER
1
ARCHITECTURAL OVERVIEW
1.1 Élan™SC520 MICROCONTROLLER
The Élan™SC520 microcontroller is a full-featured microcontroller developed for the
general embedded market. The ÉlanSC520 microcontroller combines a 32-bit, low-voltage
Am5
x
86 CPU with a complete set of integrated peripherals suitable for both real-time and
PC/AT-compatible embedded applications.
An integrated PCI host bridge, SDRAM controller, enhanced PC/AT-compatible peripherals,
and advanced debugging features provide the system designer with a wide range of on-
chip resources, allowing support for legacy devices as well as new devices available in the
current PC marketplace.
Designed for medium- to high-performance applications in the telecommunications, data
communications, and information appliance markets, the ÉlanSC520 microcontroller is
particularly well suited for applications requiring high throughput combined with low latency.
1.1.1 Distinctive Characteristics
■ Industry-standard Am5
x
86® CPU with floating point unit (FPU) and 16-Kbyte write-back
cache
– 100-MHz and 133-MHz operating frequencies
– Low-voltage operation (core V
CC
= 2.5 V)
– 5-V tolerant I/O (3.3-V output levels)
■ E86™ family of x86 embedded processors
– Part of a software-compatible family of microprocessors and microcontrollers well
supported by a wide variety of development tools
■ Integrated PCI host bridge controller leverages standard peripherals and software
– 33 MHz, 32-bit PCI bus Revision 2.2-compliant
– High-throughput 132-Mbyte/s peak transfer
– Supports up to five external PCI masters
– Integrated write-posting and read-buffering for high-throughput applications
■ Synchronous DRAM (SDRAM) controller
– Supports 16-, 64-, 128-, and 256-Mbit SDRAM.
– Supports 4 banks for a total of 256 Mbytes.
– Error Correction Code provides system reliability.
– Buffers improve read and write performance.
■ AMDebug technology offers a low-cost solution for the advanced debugging
capabilities required by embedded designers.
– Allows instruction tracing during execution from the Am5
x
86 CPU’s internal cache
– Uses an enhanced JTAG port for low-cost debugging

Table of Contents