Synchronous Serial Interface
22-6 Élan™SC520 Microcontroller User’s Manual
Figure 22-6 SSI Clock Phase and Clock Idle State: Effects on Data
22.5.3.1 4-Bit Read Cycle
A 4-bit operation can be simulated by ignoring four of the eight bits transferred. Figure 22-7
shows an example of a 4-bit read operation.
1. A full-duplex SSI command is executed in non-inverted phase, non-inverted clock, and
MSBF modes.
2. The first four bits on SSI_DO transmit a slave nibble read command.
3. The last four bits on SSI_DO can specify a four-bit NOP command, if they are not ignored
by the slave.
4. The first four bits on SSI_DI are shifted in, but can be ignored by software.
5. The last four bits on SSI_DI are the requested nibble.
6. The SSI transaction is complete one-half the SSI_CLK period after the last read edge.
Figure 22-7 SSI 4-Bit Read Cycle: Full-Duplex, Non-Inverted Phase, Non-Inverted Clock
PIOx
SSI_DI
SSI_DO
SSI_CLK
SSI_CLK
SSI_CLK
SSI_CLK
PHS_INV_ENB=0
PHS_INV_ENB=1
PHS_INV_ENB=1
PHS_INV_ENB=0
Write
Read
Transaction complete,
three-state SSI_DO
CLK_INV_ENB=0
CLK_INV_ENB=1
CLK_INV_ENB=0
CLK_INV_ENB=1
MSB
LSB
PIOx
SSI_CLK
SSI_DO
SSI_DI
MSB
LSB
To Next Page
Loading...