AMD Elan SC520 - GP Bus Echo Mode; GP-DMA Read with Cache Hit

GP Bus DMA Controller
Élan™SC520 Microcontroller User’s Manual 14-17
14.5.5.2 GP-DMA Read with Cache Hit
Figure 14-7 shows a read transfer with a cache hit (write-back cache).
Figure 14-7 GP-DMA Read Transfer with Cache Hit (Write-Back Cache)
14.5.6 GP Bus Echo Mode
When GP bus echo mode is enabled, GPAEN is driven high during accesses from the
Am5
x
86 CPU to internal peripherals to prevent external devices from decoding (or
responding to) these internal peripheral accesses. In normal operation (GP bus echo mode
disabled), the GP bus controller never asserts GPAEN.
However, accesses initiated by the GP bus DMA controller are not affected by enabling the
GP bus echo mode, and therefore the GP bus DMA controller still asserts GPAEN as it
does during normal operation. During an internal GPDMA access in GP bus echo mode,
the external GP bus commands, GPIORD
, GPMEMRD, GPIOWR, GPMEMWR, are not
asserted. However, GPAEN is still asserted. For additional information about this mode,
see “GP Bus Echo Mode” on page 13-10.
GPDACKx
daddr[27:0]
GPAEN
GPIOWR,
GPD15 – GPD0
GPTC
dmemr
GPDRQx
Address Valid
Data Valid
eads
hitm
hold
hlda
GPDBUFOE
GPMEMWR