AMD Elan SC520 - Figure 10-2 Detailed Block Diagram of SDRAM Controller

SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-3
Figure 10-2 Detailed Block Diagram of SDRAM Controller
Notes:
SDRAM controller trace and test logic is not shown.
MA12–MA0
MECC6–MECC0
SDQM3–SDQM0
CLKMEMOUT
CLKMEMIN
SCASB
–SCASA
SRASB–SRASA
SWEB – SWEA
MD31–MD0
SCS3
–SCS0
Page/Bnk
x5_addr[27–2]
MA Gen.
Control
x5_control
66-MHz PLL
Write Buffer
be3
–be0
x5_be[3–0]
data[31–0]
x5_data[31–0]
Read Buffer
ECC
Check
ECC
Gen.
x5_data[31–0]
33 MHz
BA1–BA0
Élan™SC520 Microcontroller
32 kHz
Interrupts