Watchdog Timer
19-6 Élan™SC520 Microcontroller User’s Manual
Although both the Watchdog Timer Count High and Low registers can be read from a single
32-bit CPU instruction, 32-bit accesses are split into two 16-bit accesses. If it is necessary
to read an accurate 32-bit value from the Watchdog Timer Counter, see Chapter 17,
“General-Purpose Timers”, for suggestions on dealing with this issue.
19.5 INITIALIZATION
At power-on reset, the watchdog timer is disabled. Software must enable it by setting the
ENB in the Watchdog Timer Control (WDTMRCTL) register. The watchdog timer time-out
count defaults to the maximum value. The WRST_ENB bit is set for generation of system
reset upon time-out. See “Configuration Information” on page 19-3.
Note that the processor does not resample external pins during a watchdog timer-generated
system reset. This means that the System Board Information (SYSINFO) register (MMCR
offset D70h), BOOTCS
data bus width, and BOOTCS data bus select parameters do not
change when a watchdog timer system reset occurs. All other activities are identical to
those of a normal system reset.
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