System Initialization
3-4 Élan™SC520 Microcontroller User’s Manual
In contrast, real-mode code cannot access physical memory above 0010FFEFh (the real-
mode addressing limit), and thus cannot access the default location of the MMCR. This
problem is easily resolved by programming the Configuration Base Address (CBAR)
register (Port FFFCh) to place the MMCR at an address somewhere below the real-mode
addressing limit. This allows real-mode initialization code to directly access the MMCR.
This is done in step 3 of the BIOS initialization sequence.
Note: Programming the
Configuration Base Address (CBAR) register
can place the MMCR
at an address other than its default. However, the MMCR region is always accessible at its
default location of FFFEF000h, regardless of how the CBAR register is programmed.
3.1.4 Reset Event
The ÉlanSC520 microcontroller has three primary classes of resets.
■ System reset (often called a hard reset or power-on reset)
■ System reset with SDRAM retention (called programmable reset)
■ Soft reset (often called warm start)
For more information on resetting the ÉlanSC520 microcontroller, see Chapter 6, “Reset
Generation”, and “Initialization” on page 7-5.
Often, systems have a hardware reset button or other external devices that can cause a
reset. For the ÉlanSC520 microcontroller, all of these cause a system reset. However, there
are many ways to implement external reset logic. After a reset (of any kind), boot software
can determine what caused the reset by examining various status bits.
A common and effective method of handling a reset is to determine the cause of the reset
and record the event in the CMOS memory, or in some other non-volatile memory such as
an EEPROM, non-volatile DRAM, or Flash. Debugging or diagnostic software could then
examine and report the causes of the last few resets. This can be very helpful when trying
to determine the cause of system problems. Note that the system could record other
information as well; the time and date of the reset event is a good example.
When a system reset occurs (regardless of the source) internal registers and logic blocks
are set to their power-on reset state. Therefore, if a system reset occurs, the boot software
must initialize the system from scratch.
There is one exception to this, called
programmable reset
. This function is enabled via the
PRG_RST_ENB bit in the Reset Configuration (RESCFG) register (MMCR offset D72h).
If this bit is set, assertion of the PRGRESET pin, SYS_RST bit, watchdog timer system
reset event, or AMDebug technology system reset event while PWRGOOD is asserted will
result in a system reset in which the SDRAM configuration (SDRAM type, number of banks,
refresh rate, etc.) is maintained so that the contents of SDRAM are preserved. SDRAM
controller parameters retained include the SDRAM type, number of banks, refresh rate,
and signal drive strength. This feature allows the system to be reset while guaranteeing
that the contents of SDRAM are not disturbed. This can be very valuable for system
debugging or for systems that require minimal startup time. This reset condition can be
detected by software. Note that, once programmable reset has been enabled, all system
resets other than PRWGOOD deassertion are converted to this type.
When a soft reset occurs, the system may be able to restart if the operating system saved
enough state information. For example, an old 80286-style operating system (e.g., OS/2)
causes a processor reset in order to return to real mode and call 16-bit BIOS routines.
Note: It is important to understand that, for most systems, a soft reset does not need to
be handled much differently than a system reset. For example, a system that does not need
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