Watchdog Timer
Élan™SC520 Microcontroller User’s Manual 19-3
19.4 OPERATION
The watchdog timer (WDT) can be used to regain control of the system when software fails
to respond as expected. The watchdog timer should be used in systems that require a
guaranteed recovery time from a software error.
When the watchdog timer is enabled, the counter is reset to zero automatically and starts
counting. The count increments once for every 33-MHz clock cycle. While enabled, the
software can reset the counter to zero at anytime by writing a clear keyed sequence as
described in “Keyed Sequences” on page 19-3. If the software is unable to reset the counter
before it reaches the time-out count, the watchdog timer generates an interrupt and/or a
system reset.
■ The watchdog timer can be configured to cause
either
an interrupt (maskable or non-
maskable) or a system reset upon time-out.
■ The watchdog timer can also be configured to generate
both
an interrupt and a system
reset. In this mode, the watchdog timer generates an interrupt, then starts itself over. If
it times out a second time, it generates a system reset.
A distinct keyed sequence is required to open up the Watchdog Timer Control
(WDTMRCTL) register (MMCR offset CB0h) before writes. This prevents errant code from
disabling or otherwise modifying the watchdog timer behavior. The same keyed sequence
is always used for unlocking the watchdog timer control registers.
19.4.1 Configuration Information
19.4.1.1 Keyed Sequences
All writes to the Watchdog Timer Control (WDTMRCTL) register must be preceded by a
distinct keyed sequence.
■ A data pattern of 3333h, followed by a write of CCCCh, to the Watchdog Timer Control
(WDTMRCTL) register opens up the register for a single write.
The value of the key is not written to the register but is used by internal logic to open the
register for writing. Once the ENB bit is set in the Watchdog Timer Control (WDTMRCTL)
register, a subsequent keyed sequence is required to allow any further writes to this register.
While enabled, the software can reset the counter to 0 at anytime by writing a keyed
sequence to clear the counter.
■ A data pattern of AAAAh, followed by a write of 5555h, to the Watchdog Timer Control
(WDTMRCTL) register resets the counter.
The key itself resets the counter; no further writes are necessary. It should be noted that
this clear-count key cannot be initiated while the write key is active. This would result in the
value of AAAAh being written to the register.
Watchdog Timer Count High WDTMRCNTH CB4h Bits 30–16 of the WDT current count
Watchdog Timer Interrupt
Mapping
WDTMAP D42h WDT interrupt mapping
Reset Status RESSTA D74h Reset source status: watchdog timer time-out
Table 19-1 Watchdog Timer Registers—Memory-Mapped (Continued)
Register Mnemonic
MMCR
Offset
Address Function
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