AMD Elan SC520 - Rising Edge of JTAG_TCK; When the TAP Controller Is in this State and a Rising Edge Is Applied to JTAG_TCK, the

Boundary Scan Test Interface
Élan™SC520 Microcontroller User’s Manual 25-17
25.4.3.1.8 Exit2-DR State
This is a temporary state. While in this state, if JTAG_TMS is held High, a rising edge
applied to JTAG_TCK causes the controller to enter the Update-DR state, which terminates
the scanning process. If JTAG_TMS is held Low and a rising edge is applied to JTAG_TCK,
the controller enters the Shift-DR state.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
25.4.3.1.9 Update-DR State
The Boundary Scan register is provided with a latched parallel output to prevent changes
at the parallel output while data is shifted in response to the EXTEST and SAMPLE/
PRELOAD instructions. When the TAP controller is in this state and the Boundary Scan
register is selected, data is latched onto the parallel output of this register from the
shift-register path on the falling edge of JTAG_TCK. The data held at the latched parallel
output does not change other than in this state.
All shift-register stages in a test data register selected by the current instruction retain their
previous values during this state. The instruction does not change in this state.
When the TAP controller is in this state and a rising edge is applied to JTAG_TCK, the
controller enters the Select-DR State if JTAG_TMS is held High or the Run-Test/Idle State
if JTAG_TMS is held Low.
25.4.3.1.10 Select-Instruction Register (IR)-Scan State
This is a temporary controller state. The test data register selected by the current instruction
retains its previous state. If JTAG_TMS is held Low and a rising edge is applied to
JTAG_TCK when in this state, the controller moves into the Capture-IR state and a scan
sequence for the Instruction register is initiated. If JTAG_TMS is held High and a rising
edge is applied to JTAG_TCK, the controller moves to the Test-Logic-Reset state.
The instruction does not change in this state.
25.4.3.1.11 Capture-IR State
In this controller state, the shift register contained in the Instruction register loads the fixed
value 0001b on the rising edge of JTAG_TCK.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
When the controller is in this state and a rising edge is applied to JTAG_TCK, the controller
enters the Exit1-IR state if JTAG_TMS is held High, or the Shift-IR state if JTAG_TMS is
held Low.
25.4.3.1.12 Shift-IR State
In this state, the shift register contained in the Instruction register is connected between
JTAG_TDI and JTAG_TDO and shifts data one stage towards its serial output on each
rising edge of JTAG_TCK.
The test data register selected by the current instruction retains its previous value during
this state. The instruction does not change in this state.
When the controller is in this state and a rising edge is applied to JTAG_TCK, the controller
enters the Exit1-IR state if JTAG_TMS is held High, or remains in the Shift-IR state if
JTAG_TMS is held Low.