ROM/Flash Controller
12-14 Élan™SC520 Microcontroller User’s Manual
The lowest latency times can be achieved if fast 32-bit ROMs are implemented for Execute-
In-Place (XIP) operating systems or for data structures that are accessed frequently. This
ensures a rapid data transfer, which frees up the SDRAM resource for access by other
masters.
For example, if four doublewords are accessed from a 2-1-1-1 advanced page-mode ROM,
five clock cycles are required to load this data. However, loading the same amount of data
from an 8-bit, non-page-mode ROM results in 48 clock cycles, assuming two wait states
per ROM access. While the first approach promises reasonable performance, the latter
imposes a latency that is possibly unacceptable.
12.6 INITIALIZATION
The ROM controller is connected to the ÉlanSC520 microcontroller’s system reset.
The system designer must define the boot ROM configuration devices connected to
BOOTCS
using pinstrapping. The CFG2–CFG0 pins provided on the ÉlanSC520
microcontroller are latched at the assertion of PWRGOOD to define the location and data
width of the boot device, as shown in Table 12-6.
■ CFG2 defines whether the boot device is located on the SDRAM data bus or GP bus
data bus.
■ CFG1–CFG0 define the data width of the boot device.
■ BOOTCS is forced active at system reset. Boot code must then initialize a Programmable
Address Region (PAR) register to decode the required space for the boot ROM device.
See “External ROM Devices” on page 3-17 for examples.
Non-boot devices that exist on ROMCS1 and ROMCS2 do not require pinstrapping and
are configured with the ROM configuration registers.
At system reset, the ROM controller is enabled for BOOTCS
only. The following steps
should be taken to further configure BOOTCS
and/or to enable other ROM devices.
1. Configure the ROM width, mode, access timing, and location in the BOOTCS
Control
(BOOTCSCTL) register (MMCR offset 50h), the ROMCS1
Control (ROMCS1CTL)
register (MMCR offset 54h), and/or the ROMCS2
Control (ROMCS2CTL) register
(MMCR offset 56h).
2. Set up the address range and the cacheability control, write protection, and code
execution control attributes for the BOOTCS
device or the ROMCSx device in the PAR
registers.
Table 12-6 CFGx Pinstrap Configuration Options for BOOTCS
CFG2 CFG1 CFG0 BOOTCS Data Width BOOTCS Location
0008-bit GP bus
0 0 1 16-bit GP bus
1 0 0 8-bit SDRAM bus
1 0 1 16-bit SDRAM bus
11x (don’t care) 32-bit SDRAM bus
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