SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-29
When the write buffer is enabled, writes to SDRAM occur independently of any associated
master activity until the write buffer is empty. Since the SDRAM data bus may be shared
with the ROM/Flash controller, write-buffer writes may request concurrently with master
requests to ROM/Flash. Should these two independent activities concurrently request
access to the data bus, the ROM/Flash cycle takes precedence over the write-buffer write
in favor of satisfying the requesting master. However, a ROM/Flash cycle may be
temporarily delayed should a master request ROM/Flash access during a write-buffer write
in progress. Furthermore, a ROM/Flash access that occurs during a read-ahead prefetch
results in the ROM/Flash access being temporarily delayed until the read prefetch
completes. See Chapter 12, “ROM/Flash Controller”, for information on ROM/Flash sharing
the SDRAM data bus.
ECC results in additional latencies due to required read-modify-write cycles. The read-
modify-write cycles are necessary when incomplete doublewords are written to the SDRAM
devices (i.e., any writes less than four bytes). Read-modify-write is required to update the
ECC code to include the information reflected in the partial doubleword to be written.
However, a partial doubleword write to a write-protected region does not generate a read-
modify-write cycle.
Prior to a write, the following sequence occurs:
1. The complete doubleword and ECC code is read from SDRAM and checked for errors
(the respective interrupt is generated if an error is detected)
2. The new ECC code is generated to include the data just read and the new data to be
written.
3. The complete modified doubleword and modified ECC code is written back into the
SDRAM.
Should the write cycle be a complete doubleword, the ÉlanSC520 microcontroller does not
require a read of the SDRAM first. This reduces the overhead associated with 32-bit writes
to SDRAM. However, since a read is not performed prior to a doubleword write, the contents
in SDRAM are not checked prior to the data being written.
10.6 INITIALIZATION
10.6.1 Programmable Reset
The ÉlanSC520 microcontroller’s SDRAM controller provides the capability to maintain the
contents of the SDRAM during a reset event. In effect, two types of reset are supported:
■ System reset—A complete reset where the entire SDRAM controller is reset and
contents of the SDRAM devices are lost.
■ Programmable reset—The SDRAM controller configuration is maintained and the
contents of the SDRAM devices are also maintained by maintaining refresh cycles
throughout the programmable reset duration.
Selection of the reset type is controlled by the PRG_RST_ENB bit in the Reset Configuration
(RESCFG) register (MMCR offset D72h). With this bit, the PRGRESET pin can be
programmed to reset the ÉlanSC520 microcontroller for a programmable reset. On power-
up, the PRGRESET pin is disabled and must be programmed to be operational.
See “System Reset with SDRAM Retention” on page 6-6 for detailed information on the
sources of these resets.
The purpose of the programmable reset in the memory controller is to maintain the state
of the SDRAM during an ÉlanSC520 microcontroller reset. This requires SDRAM refreshes
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