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AMD Elan SC520 - Specifying Pages and Regions

AMD Elan SC520
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System Initialization
Élan™SC520 Microcontroller Users Manual 3-9
3.7.1 Specifying Pages and Regions
For memory-mapped address regions, the Region Size/Start Address (SZ_ST_ADR) bit
field in the PAR registers specifies the number of 64-Kbyte or 4-Kbyte pages for the region.
Regions using a 64-Kbyte page size can have up to 2048 pages, for a maximum size of
128 Mbytes. Regions using a 4-Kbyte page size can have up to 128 pages, for a maximum
size of 512 Kbytes.
To specify the number of pages for a region, the value (page count minus 1) is
programmed into the SZ_ST_ADR field of the PAR register.
For example, to specify a 16-Kbyte region using a 4-Kbyte page size, the value 03h
(0000011b) would be programmed into bits 24–18 of a PAR register, i.e., one less
than the required number of pages.
To specify a page count of one, all the bits in the SZ_ST_ADR field for a PAR register
should be cleared to 0.
To specify the maximum number of pages, either 2048 or 128, all the bits in the
SZ_ST_ADR field should be set to 1.
To specify the 4-Kbyte page size, the Page Size (PG_SZ) bit should be cleared to 0.
For a 64-Kbyte page size, it should be set to 1.
The same holds true for GP bus I/O-mapped regions. The region size field specifies the
number of bytes in the addressable region. For example, to specify a region size of 8 bytes,
the value 07h (0111b) should be programmed into the SZ_ST_ADR field of the PAR register.
Note: For GP bus I/O-mapped regions, the PAR registers’ PG_SZ bit is ignored. In general,
it should be cleared to 0 for GP bus I/O regions.

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