AMD Elan SC520 - CPU Arbitration Protocol; CPU Bus Arbiter; Figure 8-2 Skipped Master Example

System Arbitration
Élan™SC520 Microcontroller User’s Manual 8-5
8.4.2 CPU Bus Arbiter
The CPU bus arbiter controls access to the internal CPU bus. This internal bus allows for:
■ Am5
x
86 CPU access of SDRAM, GP bus, PCI, or ROM
■ GP-DMA access of SDRAM
■ PCI host bridge access of SDRAM for external PCI master cycles
No concurrent operation is allowed on the CPU bus (e.g., Am5
x
86 CPU accessing the GP
bus while the PCI host bridge is accessing SDRAM). At any time, only one master is granted
access to the CPU bus.
8.4.2.1 CPU Arbitration Protocol
The CPU bus arbiter implements a rotating priority algorithm that guarantees each bus
master a place in the arbitration rotation. A master becomes lowest priority in the queue
when it receives a bus grant. A master is skipped in the rotation if its request is not asserted,
but a lower priority master request is asserted. In this case, the skipped master becomes
lowest priority as if it had been serviced (see Figure 8-2).
Figure 8-2 Skipped Master Example
In the example shown in Figure 8-2, assume that M0 has just finished a transaction. In this
case, the next master in the rotating priority queue would be M1. M1, however, is not
requesting the bus, and M2 (a lower priority master at this time) is requesting the bus. In
this case, M1 is skipped and the bus is granted to M2. M1 is the lowest priority master in
the rotation after being skipped, as if it had been granted the bus. After M2 finishes its
transaction, M0 becomes the highest priority master.
The rotating queue for the CPU bus can be seen in Figure 8-3. The Am5
x
86 CPU is the
default owner when no master is requesting the CPU bus and following reset. The host
bridge becomes a bus requestor when it has posted write data from a PCI bus master, or
it needs to perform a SDRAM read for a PCI bus master.
M0
M1
M2
REQ=1
REQ=0
Rotating Priority Queue
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Notes:
Priority: M0, M2, M0, M1, M2, M0, M1, M2, ...