Élan™SC520 Microcontroller User’s Manual 8-1
CHAPTER
8
SYSTEM ARBITRATION
8.1 OVERVIEW
The ÉlanSC520 microcontroller includes two arbiters. A CPU bus arbiter arbitrates between
the Am5
x
86 CPU, the PCI host bridge, and the GP-DMA controller on the internal CPU
bus. A PCI bus arbiter arbitrates between the Am5
x
86 CPU and up to five external PCI
masters on the external PCI bus. The system arbiter complies with
PCI Local Bus
Specification,
Revision 2.2, and complies with PCI bus transaction ordering rules.
Features of the arbitration subsystem include:
■ Supports up to five external PCI bus masters
■ Supports concurrent and nonconcurrent operating modes:
– Concurrent arbitration mode allows PCI bus arbitration to occur independently of CPU
bus arbitration, supporting peer-to-peer operation on PCI bus simultaneously with
CPU access of memory and GP bus.
– Nonconcurrent arbitration mode forces all masters to automatically acquire ownership
of both PCI and CPU buses, regardless of destination of the cycles.
■ PCI bus arbiter supports two queues with rotating priority for bus mastership:
– High-priority queue supports two bus masters maximum, any masters can be
programmed to the high-priority queue.
– Low-priority queue contains all masters not assigned to the high-priority queue.
■ CPU priority is programmable to automatically achieve bus ownership following every
one, two, or three PCI-bus-master tenures.
■ Option for PCI bus parking on CPU or on last master in concurrent arbitration mode
■ PCI bus master request/grant pairs can be individually masked in a separate control
register.
■ CPU bus arbiter provides an automatic Am5
x
86 CPU bypass that allows continued PCI
bus and GP-DMA access of SDRAM during Am5
x
86 CPU clock changes and PLL
stabilization periods.
8.2 BLOCK DIAGRAM
Figure 8-1 shows a block diagram of the system arbiter.
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