Am5
x
86
®
CPU
7-6 Élan™SC520 Microcontroller User’s Manual
bits in the Am5
x
86 CPU’s machine status (CR0) register, and the Am5
x
86 CPU’s write
buffers retain the values they had prior to the soft reset.
A soft reset event clears the NMI_ENB bit in the Interrupt Control (PICICR) register,
disabling NMIs. This allows software to initialize the stack pointer before setting the
NMI_ENB bit again after a soft reset.
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