AMD Elan SC520 - Cpu; System Reset; Table 6-3 Élansc520 Microcontroller Reset Sources

Reset Generation
6-4 Élan™SC520 Microcontroller User’s Manual
6.5.1 System Reset
System reset on the ÉlanSC520 microcontroller can be initiated by any of the following
reset events :
■ PWRGOOD pin assertion
■ Software writes to the SYS_RST bit in the Reset Configuration (RESCFG) register
(MMCR offset D72h)
■ AMDebug system reset event
■ Watchdog timer time-out event that is enabled to generate a system reset
On system reset, the following sequence of events occurs.
1. A system reset event is asserted.
2. Internal CPU, ÉlanSC520 microcontroller internal registers, system GP bus, and PCI
bus resets are asserted.
3. The system reset event is deasserted. If PWRGOOD was the source of the reset,
configuration and system board data are latched on the CFG3–CFG0 and RSTLD7–
RSTLD0 pins, respectively.
4. An RTC reset is generated if the RTC voltage monitor has detected a low RTC battery
condition
and the system reset source was PWRGOOD.
5. Internal PLL start-up time is allowed to pass.
6. Internal CPU, system GP bus, and PCI bus resets are deasserted.
The duration of the system reset is on the order of 10 ms, the start-up time of the internal
PLLs. The GPRESET and RST
pins are asserted for the 10-ms interval.
In response to the hard CPU reset, all internal Am5
x
86 CPU registers return to their reset
state, and the contents of the CPU cache are discarded. For further information on hard
Table 6-3 Élan™SC520 Microcontroller Reset Sources
Source
CPU
(Hard/Soft)
GPRESET
Pin
RST
Pin
(PCI)
Internal
Registers Notes
PWRGOOD pin Hard ✔✔✔
PRGRESET pin Hard ✔✔✔
1
,
2
Notes:
7KH35*B567B(1%ELWPXVWEHVHWWRHQDEOHWKHUHVHWIXQFWLRQ RQWKLVSLQ
,IWKH35*B567B(1%ELWLVVHWWKH6'5$0FRQWUROOHUFRQILJXUDWLRQLVPDLQWDLQHGWRVXSSRUWV\VWHPUHVHWLQZKLFK
6'5$0FRQWHQWVDUHDOVRPDLQWDLQHG
SYS_RST bit, RESCFG register Hard ✔✔✔
2
Watchdog timer reset event Hard ✔✔✔
2
AMDebug system reset Hard ✔✔✔
2
CPU_RST bit, SYSCTLA register (Port 0092h) Soft
SCP soft reset, SCPCMD register (Port 0064h) Soft
CPU shutdown (typically caused by a triple fault) Soft
GP_RST bit, RESCFG register ✔
PCI_RST bit, HBCTL register ✔