System Initialization
Élan™SC520 Microcontroller User’s Manual 3-5
to explicitly perform a soft restart will simply cause a system reset when a soft reset is
detected.
Note that the watchdog timer can generate an interrupt (maskable or non-maskable) or a
system reset, or both. Handling watchdog timer time-outs can be complex. For more
information on how the WDT operates, see Chapter 19, “Watchdog Timer”.
3.1.5 Reset Vector and Reset Segment
Immediately after a hard or soft reset, the Am5
x
86 CPU core begins execution in real mode
at the address F000:FFF0. This real-mode address is called the
reset vector
. While the
reset vector is a real-mode address, it is a redirection of the physical address FFFFFFF0h,
which is located at the top physical address of the memory device selected by BOOTCS
.
This device is called the
boot ROM device
.
After a hard or soft reset, the 64-Kbyte physical address space from FFFF0000 to
FFFFFFFFh (resident in the boot ROM device) is redirected into real-mode address space
from F000:0000 to F000:FFFF. This real-mode region is called the
reset segment
. The
region in the boot ROM device is called the
reset region
. The code that resides in this area
is called the
reset handler
.
This redirection is not performed by the addressing unit, but is an artifact of the values
programmed into the CS descriptor cache by the CPU at reset time. After any reset, the
CPU core sets the base value of CS Descriptor Cache register to FFFF0000h with a limit
of 0000FFFFh (64 Kbytes). The processor CS:EIP register pair is set to F000:0000FFF0.
The redirection works because, in real mode, linear addresses for code fetches are
generated by taking the offset in EIP and adding it to the contents of the base register in
the CS descriptor cache. Since the paging unit is disabled at reset, these linear addresses
map directly to physical addresses.
This simple mechanism causes both the redirection of the reset code region to the reset
segment and the first instruction fetch to occur from the reset vector.
Note that none of the other segment registers (and internal descriptor registers) have this
behavior. This behavior is
only
applicable to the CS Segment register and its internal
descriptor cache. For more information on the configuration of the processor registers at
reset, see the
Am486
®
DX/DX2 Microprocessor Hardware Reference Manual
, 1994 (order
#17965).
What this means is that the artificial reset segment redirection is only active until the CPU
executes a Far Jump (JMP) instruction. This is because a Far Jump instruction causes the
CS Segment register to be reloaded. When a segment register is loaded in real mode, the
processor sets the value of the corresponding descriptor cache base register to 16 times
the new value of the segment register. Since the processor is running in real mode, the
internal CS Descriptor registers are set to their normal real-mode values.
Since the reset vector is at F000:FFF0, there are only 16 bytes before the end of the
segment. That is only enough for a few instructions. So, regardless of how much (or how
little) the reset code does, the instruction at the reset vector must be a
Near Jump
into the
reset region.
For example, as shown in Figure 3-1, if the reset handler is large, then the initial Near Jump
could be to F000:0000.
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