AMD Elan SC520 - Access Timing; Operating Mode; ROM Control and Timing Configuration; ROM Location

ROM/Flash Controller
Élan™SC520 Microcontroller User’s Manual 12-7
12.5.2 ROM Control and Timing Configuration
The ÉlanSC520 microcontroller provides ROM device configuration per chip select for the
following:
■ ROM location (on GP data bus or SDRAM data bus)
■ ROM width (8, 16, or 32 bits)
■ Operating mode (page-mode or non-page-mode)
■ Access timing
12.5.2.1 ROM Location
The GP bus address is always used for the ROM address, but the ROM data bus can be
connected to either the GP bus data bus or the SDRAM data bus.
For the boot device (BOOTCS
), the CFG2 pinstrap is used to determine which of the two
buses is used for the ROM data bus. For all other ROM devices (ROMCS1
and ROMCS2),
this configuration information must be programmed by the initialization software.
■ The DGP bit in the BOOTCS Control (BOOTCSCTL) register (MMCR offset 50h)
contains the value latched from the CFG2 pinstrap when the PWRGOOD pin is asserted.
■ The DGP bit in the ROMCS1 and ROMCS2 control registers is used to configure the
location of the ROM devices enabled by these two chip selects.
12.5.2.2 ROM Width
ROM device widths of 8 bits, 16 bits, and 32 bits are supported.
The CFG1–CFG0 pinstraps are used to determine the width of the boot device (BOOTCS
).
For all other ROM devices (ROMCS1
and ROMCS2), this configuration information must
be programmed by the initialization software.
■ The WIDTH bit field in the BOOTCS Control (BOOTCSCTL) register contains the value
latched from the CFG1–CFG0 pinstraps when the PWRGOOD pin is asserted.
■ The WIDTH bit field in the ROMCS1 and ROMCS2 control registers is used to configure
the width of the ROM devices enabled by these two chip selects.
12.5.2.3 Operating Mode
The MODE bit in the control registers provided for each chip select signal is used to program
the operating mode of the associated device.
According to the different data delivery rates, the following operation modes are
distinguished:
■ Non-page mode—Characterized as having the same access time for all cycles.
Figure 12-4 shows a ROM that is capable of three wait state operation.
■ Page mode—Provides faster timing for subsequent data that falls within the page-size
of the ROM device. Figure 12-5 shows an advanced page-mode ROM that is capable
of one wait state for the first access and zero wait states for subsequent accesses.
If an unaligned access to a page-mode device is executed, i.e., when not all data are located
in the same ROM page, a new page has to be opened, which imposes an additional delay
(see Figure 12-6). Random access within a page is not supported.