System Address Mapping
4-16 Élan™SC520 Microcontroller User’s Manual
the CPU performs I/O accesses to the UART address regions, the cycles will be forwarded
out to the external GP bus. Also, the Super I/O is a positive decoding device, i.e., it does
not require a chip select because it performs the address decoding from the GP bus
addresses.
The I/O map for the Super I/O device is fragmented and may require the use of multiple
PAR registers for noncontiguous addressing, as described in Section 4.3.5.3.1. If the
fragmented I/O space unused by the Super I/O chip is not required elsewhere in the system,
then a single PAR register can be used to map the entire range of peripherals. In this case,
the UART address spaces would be the highest used I/O space internally in the ÉlanSC520
microcontroller, so the Super I/O peripherals would not be in conflict, allowing a single PAR
register to define the entire range of Super I/O peripherals from 01F0–07BEh.
See “Interfacing with a Super I/O Controller” on page 13-13, for an example of connecting
the Super I/O chip to the ÉlanSC520 microcontroller’s GP bus.
4.3.5.4 Configuring the Élan™SC520 Microcontroller for Windows
®
Compatibility
The ÉlanSC520 microcontroller can be configured to operate as a Windows compatible
microcontroller. This section describes some of the steps that may be required to configure
the memory and I/O addressing; however, this will vary depending on the requirements of
the system.
4.3.5.4.1 Memory Regions Above DOS 640-Kbyte Application Space
The ÉlanSC520 microcontroller can be programmed to accommodate the legacy PC/AT-
compatible region above the DOS 640-Kbyte application space at 000A0000h area ending
at 000FFFFFh (1 Mbyte). This space defaults to SDRAM once the SDRAM banks are
enabled, but the PAR registers can be programmed to support the various requirements
of systems requiring Windows compatibility. The list below outlines some of the steps to
consider when building a memory map in the ÉlanSC520 microcontroller system for such
compatibility.
■ Two 64-Kbyte video regions from 000A0000–000AFFFFh and 000B0000–000BFFFFh
default to SDRAM, but can be enabled as PCI bus space for PC/AT compatible video
cards on the PCI bus, via one of the PAR registers. The ÉlanSC520 microcontroller’s
PCI bus host bridge (as a target) will automatically ignore accesses in this space when
either PAR 0 or PAR 1 are programmed to overlay SDRAM regions with the PCI bus.
■ The remaining area from 000C0000–000FFFFFh is normally sub-divided in a PC/AT
system into several different address regions for BIOS, and accesses to these regions
can be redirected to either ROM, the GP bus, or the PCI bus by programming PAR
registers. Most systems will not require the use of all BIOS regions defined, since many
are for expansion ROMs intended for various plug-in cards (such as network interface
cards). The following regions are normally defined:
– One BIOS region with 64-Kbyte granularity from 000F0000–000FFFFFh
– Four extended system BIOS regions, each with 16-Kbyte granularity from
000E00000–000EFFFFFh
– 8 Expansion ROM regions, each with 16-Kbyte granularity, from 000C0000–
000DFFFFFh
4.3.5.4.2 Integrated Peripheral Mapping
Because the ÉlanSC520 microcontroller already provides standard PC/AT-compatible
peripherals that use direct I/O address mapping, there are no I/O address conflicts with
these devices. See Table 4-5 on page 4-13 for a summary of this I/O map.
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