SDRAM Controller
Élan™SC520 Microcontroller User’s Manual 10-11
10.5 OPERATION
The ÉlanSC520 microcontroller supports up to four 32-bit banks of SDRAM, with a
maximum capacity of 256 Mbytes. This integrated SDRAM controller interfaces gluelessly
to most commodity synchronous DRAM (SDRAM) devices. Mixed symmetries are
supported across all four banks.
The ÉlanSC520 microcontroller supports a column boundary method to accept a wide
variety of SDRAM devices. The
column boundary
method requires only the device’s column
address width to define the device’s page size and symmetry.
The symmetry of a device refers to its organization as defined by the number of columns
and the number of rows.
■ A device is termed
symmetric
if the number of columns and rows is equal (i.e., a square
organization).
■ A device is termed
asymmetric
if the number of rows exceeds the number of columns
(i.e., a rectangular organization). No devices exist where the number of columns exceeds
the number of rows.
The column boundary method allows the user to configure the ÉlanSC520 microcontroller
to work with 16-Mbit, 64-Mbit, 128-Mbit, and 256-Mbit SDRAM densities (both 2-bank and
4-bank internal architectures) requiring 8-bit through 11-bit column address bits.
Error Correction Code (ECC) is also supported for SDRAM devices to ensure data integrity
for these high-speed devices.
10.5.1 SDRAM Support
The ÉlanSC520 microcontroller sources a 66-MHz clock (CLKMEMOUT) to drive the
SDRAM devices. An external clock driver can be used to buffer this clock output for heavily
loaded systems. A return clock input (CLKMEMIN) is provided to control clock skew. See
“SDRAM Clocking” on page 10-6 for detailed information on SDRAM clocking. Although
the ÉlanSC520 microcontroller sources a 66-MHz clock, faster SDRAM devices are
supported (83-MHz, 100-MHz, 125-MHz, etc.).
The SDRAM controller supports 16-Mbit, 64-Mbit, 128-Mbit, and 256-Mbit SDRAM
densities with either 2-bank or 4-bank internal architectures.
■ A CAS latency (C
L
) option of either 2T or 3T is supported, where T refers to a 15-ns
clock period when a 33.333-MHz crystal is used.
■ SDRAM devices
must
be configured for a fixed
interleaved
burst length of four for reads
and
single
writes.
See “SDRAM Control Configuration” on page 10-18 for detailed information on SDRAM
configuration timing options.
The SDRAM controller services read and write requests on behalf of:
■ Am5
x
86 CPU
■ PCI masters
■ GP-DMA controller
With the exception of ECC read-modify-write cycles (due to SDRAM writes of less than a
doubleword when ECC is enabled), all read requests to SDRAM occur as a read burst of
four cycles at the interface, regardless of the amount of data requested by a master.
To Next Page
Loading...