AMD Elan SC520 - Figure 2-2 Logic Diagram by Default Pin Function

Pin Information
Élan™SC520 Microcontroller User’s Manual 2-3
Figure 2-2 Logic Diagram by Default Pin Function
1
Notes:
1. Pin names in bold indicate the default pin function. Brackets, [ ], indicate alternate, multiplexed functions. Braces, { }, indicate
pinstrap pins. Pins noted with asterisks are duplicated in this diagram to clarify which signals are used for each interface.
3&,%XV
6'5$0
6HULDO3RUWV
8$57
8$57
66,
AD31–AD0
CBE3
–CBE0
PAR
SERR
PERR
FRAME
TRDY
IRDY
STOP
DEVSEL
CLKPCIOUT
CLKPCIIN
RST
INTA–INTD
REQ4–REQ0
GNT4–GNT0
BA1–BA0
MD31–MD0
SCS3
–SCS0
CLKMEMOUT
CLKMEMIN
SRASA
–SRASB
SCASA–SCASB
SWEA–SWEB
SDQM3–SDQM0
MECC6–MECC0
SOUT2–SOUT1
SIN2–SIN1
RTS2
–RTS1
CTS1
DSR1
DTR2–DTR1
DCD1
RIN1
SSI_CLK
SSI_DO
SSI_DI
*3%XV
520)ODV
K
GPA25 {DEBUG_ENTER}
GPD15–GPD0
GPRESET
GPIORD
GPIOWR
GPMEMRD
GPMEMWR
PIO0 [GPALE]
PIO1 [GPBHE]
PIO2 [GPRDY]
PIO3 [GPAEN]
PIO4 [GPTC]
PIO5–PIO8 [GPDRQ3–GPDRQ0]
PIO9–PIO12 [GPDACK3
–GPDACK0]
PIO13–PIO23 [GPIRQ10–GPIRQ0]
PIO24 [GPDBUFOE]
PIO25 [GPIOCS16]
PIO26 [GPMEMCS16
]
-7$*
$0'HEXJ
6\VWHP7HVW
JTAG_TRST
JTAG_TCK
JTAG_TDI
JTAG_TDO
JTAG_TMS
PIO27 [GPCS0]
BOOTCS
ROMCS2–ROMCS1 [GPCS2–GPCS1]
ROMRD
FLASHWR
ROMBUFOE
CMDACK
BR/TC
STOP/TX
TRIG/TRACE
CF_DRAM [WBMSTR2] {CFG2}
DATASTRB [WBMSTR1] {CFG1}
CF_ROM_GPCS
[WBMSTR0] {CFG0}
TMRIN1–TMRIN0 [GPCS4–GPCS5]
TMROUT1–TMROUT0 [GPCS6–GPCS7]
7LPHUV
PITGATE2 [GPCS3]
PITOUT2 {CFG3}
&ORFNVDQG  5HVHW
32MXTAL2–32MXTAL1
LF_PLL1
CLKTIMER [CLKTEST]
PWRGOOD
PRGRESET
BBATSEN
GPA22–GPA15 {RSTLD7–RSTLD0}
GPA13–GPA0
GPA24 {INST_TRCE}
GPA23 {AMDEBUG_DIS}
PIO28 [CTS2]
PIO29 [DSR2
]
PIO30 [DCD2
]
PIO31 [RIN2
]
MD31–MD0*
GPA25–GPA0*
GPD15–GPD0*
MA12–MA0
32KXTAL2–32KXTAL1