Real-Time Clock
Élan™SC520 Microcontroller User’s Manual 20-11
3. Initialize the ten time, calendar, and alarm registers in either binary or BCD data format.
4. Specify the format in the data mode via the DATE_MODE bit in the RTC Control B
(RTCCTLB) register. All ten time, calendar, and alarm registers must use the same data
mode, either binary or BCD.
5. Enable updates via the SET bit in RTC Control B (RTCCTLB) register.
6. Enable the divider chain by programming 010b in the OSC_CTL field. Time and update
cycles will begin 500 ms after this write.
Steps 2 and 6 are necessary only if precision setting is required. Otherwise, the OSC_CTL
field can be written to 010b in step 2, and step 6 can be skipped. The first update cycle,
however, will occur at an undetermined time after updates are enabled.
When initialized, the RTC makes all updates in whatever data mode has been programmed.
To change the data mode, the ten data bytes must be re-initialized.
20.6.1 RTC Reset
The RTC is not automatically reset by a system reset. There are three conditions that trigger
an RTC reset:
■ BBATSEN drops below 2.0 V (sampled when PWRGOOD asserts)—During operation
from the main power supply, the backup battery voltage might drop below the trip voltage
(2.0 V). The RTC is not reset until a PWRGOOD assertion occurs.
■ Power is applied to VCC_RTC (at backup battery installation)—When the backup battery
is plugged in, the RTC is immediately reset.
■ No battery during power-up (sampled after PWRGOOD asserts)—If the system does
not contain a backup battery and the BBATSEN line potential is below 2.0 V, the RTC
is reset when PWRGOOD asserts.
Note that this RTC reset may or may not occur when a master power-on reset occurs,
depending on the state of BBATSEN.
If the BBATSEN signal drops below the 2.0-V reference and PWRGOOD is Low, an internal
RTC reset signal is generated to notify the user via the RTC_VRT bit (RTC index 0Dh) that
the RTC contents are no longer valid.
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