AMD Elan SC520 - Registers

UART Serial Ports
Élan™SC520 Microcontroller User’s Manual 21-3
Each UART supports loopback mode. In this mode, the UART’s transmitter output is
internally connected with the receiver input. It is useful for testing the operation of a local
UART channel without affecting the states of the UART output pins and independently of
the state of the UART input pins.
When in loopback mode, RTS
and DTR are internally connected to CTS and DSR,
respectively. In addition, the DTR
and RTS signals are forced inactive. Therefore, hardware
flow control is inactive.
UART interrupt requests are disabled while in loopback mode.
Table 21-2 lists the connection of DTE to DTE.
21.4 REGISTERS
The UARTs are controlled by the memory-mapped registers listed in Table 21-3 and the
direct-mapped registers listed in Table 21-4.
Table 21-2 Connection of DTE to DTE
DTE DTE
SOUT SIN
SIN SOUT
CTS
RTS
RTS CTS
DSR DTR
DTR DSR
RIN RIN
DCD DCD
Table 21-3 UART Registers—Memory-Mapped
Register Mnemonic
MMCR
Offset
Address Function
Address Decode Control ADDDECCTL 80h UART 1 and UART 2 disables
PIO31–PIO16 Pin Function
Select
PIOPFS31_16 C22h PIO or interface function select: RIN2
, DCD2,
DSR2
, CTS2
Clock Select CLKSEL C26h CLKTIMER[CLKTEST] pin enable, CLKTEST
output select options (
18.432 MHz or 1.8432
MHz
UART), CLKTIMER or CLKTEST select
UART 1 General Control
UART 2 General Control
UART1CTL
UART2CTL
CC0h
CC4h
Clock source; receive TC interrupt and transmit
TC interrupt enables
UART 1 General Status
UART 2 General Status
UART1STA
UART2STA
CC1h
CC5h
Receive TC and transmit TC interrupts status
UART 1 FIFO Control
Shadow
UART 2 FIFO Control
Shadow
UART1FCRSHAD
UART2FCRSHAD
CC2h
CC6h
Information written to the direct-mapped UART
x FIFO Control (UARTxFCR) register
UART 1 Interrupt Mapping UART1MAP D28h UART 1 interrupt mapping